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1307B 查看數據表(PDF) - Linear Technology

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1307B Datasheet PDF : 20 Pages
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LT1307/LT1307B
PI FU CTIO S
VC (Pin 1): Compensation Pin for Error Amplifier. Con-
nect a series RC from this pin to ground. Typical values
are 100kand 680pF. Minimize trace area at VC.
FB (Pin 2): Feedback Pin. Reference voltage is 1.22V.
Connect resistor divider tap here. Minimize trace area at
FB. Set VOUT according to: VOUT = 1.22V(1 + R1/R2).
SHDN (Pin 3): Shutdown. Ground this pin to turn off
switcher. Must be tied to VIN (or higher voltage) to enable
switcher. Do not float the SHDN pin.
GND (Pin 4): Ground. Connect directly to local ground
plane.
SW (Pin 5): Switch Pin. Connect inductor/diode here.
Minimize trace area at this pin to keep EMI down.
VIN (Pin 6): Supply Pin. Must have 1µF ceramic bypass
capacitor right at the pin, connected directly to ground.
LBI (Pin 7): Low-Battery Detector Input. 200mV refer-
ence. Voltage on LBI must stay between ground and
700mV.
LBO (Pin 8): Low-Battery Detector Output. Open collec-
tor, can sink 10µA. A 1Mpull-up is recommended.
BLOCK DIAGRA
VIN
6
R5
40k
VOUT
R1
(EXTERNAL)
FB
Q1
FB
2
R2
(EXTERNAL)
VIN
R6
40k
+
gm
ERROR
AMPLIFIER
Q2
×10
R3
30k
R4
140k
RAMP
GENERATOR
VC
1
+
*
BIAS
A1
SHUTDOWN
SHDN
3
LBI
7+
LBO
ENABLE
8
200mV
A4
COMPARATOR
FF
+
Σ
+
+
A2
R
Q
S
DRIVER
SW
5
Q3
600kHz
OSCILLATOR
A=3
0.15
*HYSTERESIS IN LT1307 ONLY
4
GND
1307 F02
Figure 2. LT1307/LT1307B Block Diagram
1307fa
7

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