LTC1758-2 查看數據表（PDF） - Linear Technology

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LTC1758-2

RF Power Controllers with 250kHz Control Loop Bandwidth and 40dB Dynamic Range

Linear Technology 

LTC1758-1/LTC1758-2

APPLICATIO S I FOR ATIO

LTC1758-1 Description

The LTC1758-1 is identical in performance to the

LTC1758-2 except that only one control output (VPCA) is

available. The LTC1758-1 can drive a single band (850MHz

to 2000MHz) or a dual RF channel module with an

internal mulitplexer. Several manufacturers offer dual RF

channel modules with an internal mulitplexer.

General Layout Considerations

The LTC1758-1/LTC1758-2 should be placed near the

directional coupler. The feedback signal line to the RF pin

should be a 50Ω transmission line with optional termina-

tion or a short line. If short-circuit protection is used,

bypass capacitors are required at VCC.

External Termination

The LTC1758 has an internal 200Ω termination resistor at

the RF pin. If a directional coupler is used, it is recom-

mended that an external 68Ω termination resistor be

connected between the RF coupling capacitor (33pF), and

ground at the side connected to the directional coupler. If

the termination is placed at the LTC1758 RF pin, then the

68Ω resistor must be connected to VIN since the detector

is referenced to VIN. Termination components should be

placed adjacent to the LTC1758.

Power Ramp Profiles

The external voltage gain associated with the RF channel

can vary significantly between RF power amplifier types.

The LTC1758 frequency compensation has been opti-

mized to be stable with several different power amplifiers

and manufacturers. This frequency compensation gener-

ally defines the loop dynamics that impact the power/time

response and possibly (slow loops) the power ramp

sidebands. The LTC1758 operates open loop until an RF

voltage appears at the RF pin, at which time the loop closes

and the output power follows the DAC profile. The RF

power amplifier will require a certain control voltage level

(threshold) before an RF output signal is produced. The

LTC1758 VPCA/B outputs must quickly rise to this thresh-

old voltage in order to meet the power/time profile. To

reduce this time, the LTC1758 starts at 600mV. However,

at very low power levels the PCTL input signal is small, and

the VPCA/B outputs may take several microseconds to

reach the RF power amplifier threshold voltage. To reduce

this time, it may be necessary to apply a positive pulse at

the start of the ramp to quickly bring the VPCA/B outputs to

the threshold voltage. This can generally be achieved with

DAC programming. The magnitude of the pulse is depen-

dent on the RF amplifier characteristics.

Power ramp sidebands and power/time are also a factor

when ramping to zero power. For RF amplifiers requiring

high control voltages, it may be necessary to further adjust

the DAC ramp profile. When the power is ramped down the

loop will eventually open at power levels below the LTC1758

detector threshold. The LTC1758 will then go open loop

and the output voltage at VPCA or VPCB will stop falling. If

this voltage is high enough to produce RF output power,

the power/time or power ramp sidebands may not meet

specification. This problem can be avoided by starting the

DAC ramp from 100mV (Figure 1). At the end of the cycle,

the DAC can be ramped down to 0mV. This applies a

negative signal to the LTC1758 thereby ensuring that the

VPCA/B outputs will ramp to 0V. The 100mV ramp step

must be applied at least 4µs before TXEN is asserted high

10

0

–10

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–30

–40

–50

–60

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–80

–28 –18 –10

START

PULSE

START

CODE

0

543 553 561 571

TIME (µs)

ZERO

CODE

100mV

TXEN

SHDN

50µs MINIMUM, ALLOWS TIME FOR DAC

AND AUTOZERO TO SETTLE

1758 F01

Figure 1. LTC1758 Ramp Timing

8

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