LY62L5128SV-70LLY 查看數據表（PDF） - Lyontek Inc.
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LY62L5128SV-70LLY Datasheet PDF : 17 Pages
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®
Rev. 1.7
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN
-
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
MAX
6
8
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
LY62L5128-45
MIN. MAX.
45
-
-
45
-
45
-
25
10
-
5
-
-
15
-
15
10
-
LY62L5128-55
MIN. MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
LY62L5128-70
MIN. MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYM. LY62L5128-45 LY62L5128-55
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC
45
-
55
-
Address Valid to End of Write
tAW
40
-
50
-
Chip Enable to End of Write
tCW
40
-
50
-
Address Set-up Time
tAS
0
-
0
-
Write Pulse Width
tWP
35
-
45
-
Write Recovery Time
tWR
0
-
0
-
Data to Write Time Overlap
tDW
20
-
25
-
Data Hold from End of Write Time tDH
0
-
0
-
Output Active from End of Write
tOW*
5
-
5
-
Write to Output in High-Z
tWHZ*
-
15
-
20
*These parameters are guaranteed by device characterization, but not production tested.
LY62L5128-70
MIN. MAX.
70
-
60
-
60
-
0
-
55
-
0
-
30
-
0
-
5
-
-
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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