M5M5V208AKV 查看數據表（PDF） - Renesas Electronics
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M5M5V208AKV Datasheet PDF : 8 Pages
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(4) TIMING DIAGRAMS
Read cycle
A0~ 17
S1
S2
OE
DQ1~ 8
W = "H" level
(Note 5)
(Note 5)
(Note 5)
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
tCR
ta(A)
ta (S1)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tv (A)
tdis (S1)
tdis (S2)
tdis (OE)
DATA VALID
(Note 5)
(Note 5)
(Note 5)
Write cycle (W control mode)
tCW
A0~ 17
S1
S2
OE
W
DQ1~ 8
Rev ision-A0.5
(Note 5)
(Note 5)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten (W)
ten(OE)
DATA IN
STABLE
tsu (D)
th (D)
(Note 5)
(Note 5)
5
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