M5M5V208AKV 查看數據表（PDF） - Renesas Electronics
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M5M5V208AKV Datasheet PDF : 8 Pages
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Write cycle ( S1 control mode)
A0~ 17
S1
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
tCW
tsu (A)
tsu (S1)
trec (W)
S2
(Note 5)
(Note 7)
W
(Note 5)
DQ1~ 8
Write cycle (S2 control mode)
A0~ 17
(Note 6)
tsu (D)
th (D)
DATA IN
STABLE
tCW
(Note 5)
(Note 5)
S1
S2
W
DQ1~ 8
(Note 5)
tsu (A)
tsu (S2)
trec (W)
(Note 5)
(Note 7)
(Note 5)
(Note 6)
tsu (D)
th (D)
DATA IN
STABLE
Note
5: Hatching indicates the state is "don't care".
6: Writing is executed while S2 high overlaps S1 and W low.
7: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
8: Don't apply inverted phase signal externally when DQ pin is output mode.
(Note 5)
Rev ision-A0.5
6
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