M66004FP 查看數據表（PDF） - Mitsumi

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M66004FP

16-DIGIT 5×7-SEGMENT VFD CONTROLLER

Mitsumi 

BLOCK DIAGRAM

MITSUBISHI 〈DIGITAL ASSP〉

M66004SP/FP

16-DIGIT 5×7-SEGMENT VFD CONTROLLER

Display code register

(8-bit × 16)

Chip

select input

CS 14

Shift

clock input

SCK 15

Serial

data input

SDATA

16

Serial

receive circuit

code

write

Code /

command

control circuit

RAM

write

CGROM

(35-bit × 160)

CGRAM

(35-bit × 16)

Reset

input

RESET 13

Display control

register

code select

Clock

input

XIN 21

Clock

output

XOUT 20

Clock

generator

Display controller

Segment

output circuit

59 SEG00

33 SEG26

31 SEG27

Segment

outputs

23 SEG35

Output port

(2 bits)

18 P0

17 P1

Output

ports

Digit

output circuit

12 DIG00

1 DIG11

64 DIG12

Digit

outputs

61 DIG15

OPERATION FLOW

The serial receive circuit receives 8-bit serial data, latches

the data by an internal latch signal, and then masks inputs

from the MCU.

When the code/command circuit receives a command, it sets

the display control register to the fixed state, and when it re-

ceives a character code, it writes the code to one of 16 dis-

play code registers which corresponds to the digit to display.

The display controller outputs digit ON/OFF timing pulse to

the digit output circuit and selects one character code to dis-

play among display code registers. The selected character

code is input to either CGROM decoder or CGRAM decoder

and then converted into a 35-bit character pattern to input the

segment output circuit.

2

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