MAS6179 查看數據表（PDF） - Micro Analog systems
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MAS6179 Datasheet PDF : 10 Pages
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DA6179.000
22 January, 2007
PAD LAYOUT
MAS6179Ax,
x=1, 2
VDD
QO2
QO1
QO3
QI
AGC
PDN2
OUT
VSS
RFI2
RFIM
RFIP
RFI3
PDN1
AON
DEC
1420 µm
DIE size = 1.42 x 1.80 mm; rectangular PAD 80 µm x 80 µm
Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left
floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Power Supply Voltage
Quartz Filter Output for Crystal 2
Quartz Filter Output for Crystal 1
Quartz Filter Output for Crystal 3
Quartz Filter Input for Crystals
AGC Capacitor
Power Down/Frequency Selection Input 2
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down/Frequency Selection Input 1
Receiver Input 3 (for Antenna Capacitor 3)
Positive Receiver Input
Negative Receiver Input
Receiver Input 2 (for Antenna Capacitor 2)
Power Supply Ground
Name
VDD
QO2
QO1
QO3
QI
AGC
PDN2
OUT
DEC
AON
PDN1
RFI3
RFIP
RFIM
RFI2
VSS
X-coordinate
154 µm
154 µm
154 µm
154 µm
154 µm
154 µm
154 µm
154 µm
1266 µm
1266 µm
1266 µm
1266 µm
1266 µm
1266 µm
1266 µm
1266 µm
Y-coordinate
1580 µm
1393 µm
1207 µm
1021 µm
835 µm
648 µm
462 µm
276 µm
276 µm
462 µm
648 µm
835 µm
1021 µm
1207 µm
1393 µm
1580 µm
Note
1
2
3
1
4
4
Notes:
1) PDN1 = PDN2 = VDD means receiver off
- Fast start-up is triggered when the receiver is after power down controlled to power up
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
4) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD
2 (10)
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