14521BG 查看數據表（PDF） - ON Semiconductor
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14521BG Datasheet PDF : 9 Pages
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MC14521B
8.0
4.0
VDD = 15 V
TEST CIRCUIT
FIGURE 7
0
10 V
−4.0
−8.0
5.0 V
−12
{ RTC = 56 kW,
−16 C = 1000 pF
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
−55 −25
0
25
50
75 100 125
TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY
Figure 5. RC Oscillator Stability
RS
RTC
VDD
C
VDD VDD′
IN 1 OUT 1
OUT 2
Q18
Q19
IN 2 Q20
Q21
Q22
Q23
R
Q24
VSS VSS′
100
50
20
10
5.0 f AS A FUNCTION
OF C
2.0 (RTC = 56 kW)
1.0 (RS = 120 k)
0.5
VDD = 10 V
TEST CIRCUIT
FIGURE 7
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
0.2
0.1
1.0 k
10 k
100 k
RTC, RESISTANCE (OHMS)
1.0 m
0.0001
0.001
0.01
0.1
C, CAPACITANCE (mF)
Figure 6. RC Oscillator Frequency as a
Function of RTC and C
VDD
PULSE
GENERATOR
VDD′
IN 1 Q18
Q19
Q20
Q21
IN 2 Q22
Q23
Q24
OUT 1
R OUT 2
VSS VSS
Figure 7. RC Oscillator Circuit
Figure 8. Functional Test Circuit
ÎÎÎÎFUNÎÎCTÎÎIONÎÎALÎÎTESÎÎT SÎÎEQÎÎUENÎÎCEÎÎÎÎÎÎÎÎInpÎÎutsÎÎÎÎÎÎÎÎOÎÎutpÎÎuts ÎÎÎÎÎÎÎÎÎÎÎÎCÎÎomÎÎmenÎÎts ÎÎÎÎÎÎ
Reset In 2 Out 2 VSS′ VDD′ Q18 Counter is in three 8−stage sections
thru in parallel mode Counter is reset. In 2
Q24 and Out 2 are connected together.
1
0
0
VDD GND
0
0
1
1
A test function (see Figure 8) has been included
for the reduction of test time required to exercise all
24 counter stages. This test function divides the
counter into three 8−stage sections, and 255
counts are loaded in each of the 8−stage sections
in parallel. All flip−flops are now at a logic “1”. The
counter is now returned to the normal 24−stages in
0
0
1
1
−
−
−
−
−
−
series configuration. One more pulse is entered into
Input 2 (In 2) which will cause the counter to ripple
from an all “1” state to an all “0” state.
1
1
0
0
0
0
First “0” to “1” transition on In 2,
Out 2 node.
255 “0” to “1” transitions are clocked
into this In 2, Out 2 node.
1 The 255th “0” to “1” transition.
1
1
GND
1
0
1
Counter converted back to 24−stages
in series mode.
VDD
1
0
1 Out 2 converts back to an output.
0
1
Counter ripples from an all “1” state
0 to an all “0” stage.
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