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MC34115

CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR

Motorola => Freescale 

MC34115

CIRCUIT DESCRIPTION

The continuously variable slope delta modulator (CVSD)

is a simple alternative to more complex conventional

conversion techniques in systems requiring digital

communication of analog signals. The human voice is

analog, but digital transmission of any signal over great

distance is attractive. Signal/noise ratios do not vary with

distance in digital transmission and multiplexing, switching

and repeating hardware is more economical and easier to

design. However, instrumentation A–D converters do not

meet the communications requirements. The CVSD A–D is

well suited to the requirements of digital communications and

is an economically efficient means of digitizing analog inputs

for transmission.

The Delta Modulator

The innermost control loop of a CVSD converter is a

simple delta modulator. A block diagram CVSD Encoder is

shown in Figure 11. A delta modulator consists of a

comparator in the forward path and an integrator in the

feedback path of a simple control loop. The inputs to the

comparator are the input analog signal and the integrator

output. The comparator output reflects the sign of the

difference between the input voltage and the integrator

output. That sign bit is the digital output and also controls the

direction of ramp in the integrator. The comparator is

normally clocked so as to produce a synchronous and

band–limited digital bit stream.

If the clocked serial bit stream is transmitted, received,

and delivered to a similar integrator at a remote point, the

remote integrator output is a copy of the transmitting control

loop integrator output. To the extent that the integrator at the

transmitting locations tracks the input signal, the remote

receiver reproduces the input signal. Low pass filtering at

the receiver output will eliminate most of the quantizing

noise, if the clock rate of the bit stream is an octave or more

above the bandwidth of the input signal. Voice bandwidth is

4.0 kHz and clock rates from 8.0 k and up are possible.

Thus, the delta modulator digitizes and transmits the analog

input to a remote receiver. The serial, unframed nature of

the data is ideal for communications networks. With no

input at the transmitter, a continuous one zero alternation is

transmitted. If the two integrators are made leaky, then

during any loss of contact the receiver output decays to

zero and receive restart begins without framing when the

receiver reacquires. Similarly, a delta modulator is tolerant

of sporadic bit errors. Figure 12 shows the delta modulator

waveforms while Figure 13 shows the corresponding CVSD

decoder block diagram.

The Companding Algorithm

The fundamental advantages of the delta modulator are its

simplicity and the serial format of its output. Its limitations are

its ability to accurately convert the input within a limited digital

bit rate. The analog input must be band limited and amplitude

limited. The frequency limitations are governed by the

nyquist rate while the amplitude capabilities are set by the

gain of the integrator.

The frequency limits are bounded on the upper end; that

is, for any input bandwidth there exists a clock frequency

larger than that bandwidth which will transmit the signal with

a specific noise level. However, the amplitude limits are

bounded on both upper and lower ends. For a signal level,

one specific gain will achieve an optimum noise level.

Unfortunately, the basic delta modulator has a small dynamic

range over which the noise level is constant.

The continuously variable slope circuitry provides

increased dynamic range by adjusting the gain of the

integrator. For a given clock frequency and input bandwidth

the additional circuitry increases the delta modulator’s

dynamic range. External to the basic delta modulator is an

algorithm which monitors the past few outputs of the delta

modulator in a simple shift register. The register is 3–bits

long. The accepted CVSD algorithm simply monitors the

contents of the shift register and indicates if it contains all 1s

or 0s. This condition is called coincidence. When it occurs, it

indicates that the gain of the integrator is too small. The

coincidence output charges a single–pole low pass filter. The

voltage output of this syllabic filter controls the integrator gain

through a pulse amplitude modulator whose other input is the

sign bit or up/down control.

The simplicity of the all 1s, all 0s algorithm should not be

taken lightly. Many other control algorithms using the shift

register have been tried. The key to the accepted algorithm is

that it provides a measure of the average power or level of

the input signal. Other techniques provide more

instantaneous information about the shape of the input curve.

The purpose of the algorithm is to control the gain of the

integrator and to increase the dynamic range. Thus, a

measure of the average input level is what is needed.

The algorithm is repeated in the receiver and thus the level

data is recovered in the receiver. Because the algorithm

operates only on the past serial data, it changes the nature of

the bit stream without changing the channel bit rate.

The effect of the algorithm is to compand the input signal.

If a CVSD encoder is played into a basic delta modulator, the

output of the delta modulator will reflect the shape of the input

signal but all of the output will be at an equal level. Thus, the

algorithm at the output is needed to restore the level

variations. The bit stream in the channel is as if it were from

a standard delta modulator with a constant level input.

The delta modulator encoder with the CVSD algorithm

provides an efficient method for digitizing a voice input in a

manner which is especially convenient for digital

communications requirements.

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