MCP6S22-I/P 查看數據表（PDF） - Microchip Technology
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MCP6S22-I/P Datasheet PDF : 43 Pages
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MCP6S21/2/6/8
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
Sym
Min
Typ Max Units
Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
Input Leakage Current
Logic Threshold, High
Amplifier Output Leakage Current
VIL
0
—
0.3VDD
V
IIL
-1.0
—
+1.0 µA
VIH
0.7VDD
—
VDD
V
—
-1.0
—
+1.0
µA In Shutdown mode
SPI Output (SO, for MCP6S26 and MCP6S28)
Logic Threshold, Low
Logic Threshold, High
SPI Timing
VOL
VOH
VSS
VDD-0.5
— VSS+0.4 V IOL = 2.1 mA, VDD = 5V
—
VDD
V IOH = -400 µA
Pin Capacitance
CPIN
—
10
—
pF All digital I/O pins
Input Rise/Fall Times (CS, SI, SCK)
tRFI
—
—
2
µs Note 1
Output Rise/Fall Times (SO)
CS high time
tRFO
—
5
—
ns MCP6S26 and MCP6S28
tCSH
40
—
—
ns
SCK edge to CS fall setup time
tCS0
10
—
—
ns SCK edge when CS is high
CS fall to first SCK edge setup time
tCSSC
40
—
—
ns
SCK Frequency
fSCK
—
SCK high time
tHI
40
SCK low time
tLO
40
SCK last edge to CS rise setup time
tSCCS
30
—
10
MHz VDD = 5V (Note 2)
—
—
ns
—
—
ns
—
—
ns
CS rise to SCK edge setup time
tCS1
100
—
—
ns SCK edge when CS is high
SI set-up time
tSU
40
—
—
ns
SI hold time
tHD
10
—
—
ns
SCK to SO valid propagation delay
tDO
—
—
80
ns MCP6S26 and MCP6S28
CS rise to SO forced to zero
tSOZ
—
—
80
ns MCP6S26 and MCP6S28
Channel and Gain Select Timing
Channel Select Time
Gain Select Time
Shutdown Mode Timing
tCH
—
1.5
—
µs CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS = 0.7VDD to VOUT 90% point
tG
—
1
—
µs CHx = 0.3V, G = 5 to G = 1 select,
CS = 0.7VDD to VOUT 90% point
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
Time
tON
—
3.5
10
µs CS = 0.7VDD to VOUT 90% point
Into Shutdown mode (CS goes high)
tOFF
to Amplifier Output High-Z Turn-off
Time
—
1.5
—
µs CS = 0.7VDD to VOUT 90% point
POR Timing
Power-On Reset power-up time
tRPU
—
30
—
µs VDD = VPOR - 0.1V to VPOR + 0.1V,
50% VDD to 90% VOUT point
Power-On Reset power-down time
tRPD
—
10
—
µs VDD = VPOR + 0.1V to VPOR - 0.1V,
50% VDD to 90% VOUT point
Note 1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (tDO ≤ 80 ns), data input setup time (tSU ≥ 40 ns), SCK high time (tHI ≥ 40 ns), and SCK rise and
fall times of 5 ns. Maximum fSCK is, therefore, ≈ 5.8 MHz.
DS21117A-page 4
2003 Microchip Technology Inc.
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