MCP6S22-I/P 查看數據表（PDF） - Microchip Technology

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MCP6S22-I/P

Single-Ended, Rail-to-Rail I/O, Low Gain PGA

Microchip Technology 

1.1 DC Output Voltage Specs / Model

1.1.1 IDEAL MODEL

The ideal PGA output voltage (VOUT) is:

EQUATION

VO_ideal = GVIN

VREF = VSS = 0V

where: G is the nominal gain

(see Figure 1-7). This equation holds when there are

no gain or offset errors and when the VREF pin is tied to

a low impedance source (<< 0.1Ω) at ground potential

(VSS = 0V).

1.1.2 LINEAR MODEL

The PGA’s linear region of operation, including offset

and gain errors, is modeled by the line VO_linear, shown

in Figure 1-7.

EQUATION

VO_linear = G(1 + gE)(VIN – 0.3V + VOS ) + 0.3V

VREF = VSS = 0V

The endpoints of this line are at VO_ideal = 0.3V and

VDD-0.3V. The gain and offset specifications referred to

in the electrical specifications are related to Figure 1-7,

as follows:

EQUATION

gE

=

100% ----------V----2----–----V----1-----------

G(VDD – 0.6V)

VOS

=

----------V----1----------

G(1 + gE)

G = +1

∆G ⁄ ∆TA

=

-∆---g----E-

∆TA

MCP6S21/2/6/8

VOUT (V)

VDD

VDD-0.3

V2

0.3

V1

0

0.3

0G

VIN (V)

VDD - 0.3 VDD

G

G

FIGURE 1-7:

Output Voltage Model with

the standard condition VREF = VSS = 0V.

1.1.3 OUTPUT NON-LINEARITY

Figure 1-8 shows the Integral Non-Linearity (INL) of the

output voltage.

EQUATION

INL = VOUT – VO_linear

The output non-linearity specification in the electrical

specifications is related to Figure 1-8 by:

EQUATION

VONL

=

-m----a---x---{----V----4--,---V----3---}-

VDD – 0.6V

INL (V)

V4

0

V3

0.3

0G

VIN (V)

VDD - 0.3 VDD

G

G

FIGURE 1-8:

Output Voltage INL with the

standard condition VREF = VSS = 0V.

 2003 Microchip Technology Inc.

DS21117A-page 7

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