MH8S72BAFD-7 查看數據表（PDF） - MITSUBISHI ELECTRIC

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MH8S72BAFD-7

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MITSUBISHI ELECTRIC  

MH8S72BAFD -7, -8 MITSUBISHI LSIs

P rSepl iemci.n a r y 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

PIN FUNCTION

CK0

Input

Master Clock:All other inputs are referenced to the rising

edge of CK

CKE0

Input

Clock Enable:CKE controls internal clock.When CKE is

low,internal clock for the following cycle is ceased. CKE is

also used to select auto / self refresh. After self refresh

mode is started, CKE E becomes asynchronous input.Self

refresh is maintained as long as CKE is low.

/S0,2

/RAS,/CAS,/W

Input

Input

Chip Select: When /S is high,any command means

No Operation.

Combination of /RAS,/CAS,/W defines basic commands.

A0-11

BA0-1

DQ0-63

CB0-7

DQM0-7

Vdd,Vss

REGE

Input

A0-11 specify the Row/Column Address in conjunction with

BA.The Row Address is specified by A0-11.The Column

Address is specified by A0-9.A10 is also used to indicate

precharge option.When A10 is high at a read / write

command, an auto precharge is performed. When A10 is

high at a precharge command, both banks are precharged.

Input

Bank Address:BA0,1 is not simply BA.BA0,1 specifies

the bank to which a command is applied.BA must be set

with ACT,PRE,READ,WRITE commands

Input/Output

Data In and Data out are referenced to the rising edge of

CK

Input

Din Mask/Output Disable:When DQMB is high in burst

write.Din for the current cycle is masked.When DQMB is high

in burst read,Dout is disabled at the next but one cycle.

Power Supply Power Supply for the memory mounted module.

Output

Register enable:When REGE is low,All control signals and

address are buffered. (Buffer mode) When REGE is

high,All control and address are latched. (Latch mode)

MIT-DS-0273-0.2

MITSUBISHI

ELECTRIC

1/ Dec./1998 6

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