MJW16206 查看數據表（PDF） - ON Semiconductor

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MJW16206

POWER TRANSISTORS

ON Semiconductor 

MJW16206

DYNAMIC DESATURATION

DYNAMIC DESATURATION

The SCANSWITCH series of bipolar power transistors

are specifically designed to meet the unique requirements of

horizontal deflection circuits in computer monitor

applications. Historically, deflection transistor design was

focused on minimizing collector current fall time. While fall

time is a valid figure of merit, a more important indicator of

circuit performance as scan rates are increased is a new

characteristic, “dynamic desaturation.” In order to assure a

linear collector current ramp, the output transistor must

remain in hard saturation during storage time and exhibit a

rapid turn–off transition. A sluggish transition results in

serious consequences. As the saturation voltage of the

output transistor increases, the voltage across the yoke

drops. Roll off in the collector current ramp results in

improper beam deflection and distortion of the image at the

right edge of the screen. Design changes have been made in

the structure of the SCANSWITCH series of devices which

minimize the dynamic desaturation interval. Dynamic

desaturation has been defined in terms of the time required

for the VCE to rise from 1.0 to 5.0 volts (Figures 13 and 14)

and typical performance at optimized drive conditions has

been specified. Optimization of device structure results in a

linear collector Current ramp, excellent turn–off switching

performance, and significantly lower overall power

dissipation.

tfi

90% IC(pk)

VCE

IC

VCE = 20 V

10% IC(pk)

0

tsv

0

0% IB

Figure 13. Deflection Simulator Switching

Waveforms From Circuit in Figure 15

5

VCE

4

DYNAMIC DESATURATION TIME

3

IS MEASURED FROM VCE = 1 V

TO VCE = 5 V

2

1

0

tds

TIME (ns)

Figure 14. Definition of Dynamic

Desaturation Measurement

EMITTER–BASE TURN–OFF ENERGY

Typical techniques for driving horizontal outputs rely on

a pulse transformer to supply forward base current, and a

turn–off network that includes a series base inductor to limit

the rate of transition from forward to reverse drive. An

alternate drive scheme has been used to characterize the

SCANSWITCH series of devices (see Figure 15). This

circuit produces a ramp of base drive, eliminating the heavy

overdrive at the beginning of the collector current ramp and

underdrive just prior to turnoff produced by typical drive

strategies. This high performance drive has two additional

important advantages. First, the configuration of T1 allows

LB to be placed outside the path of forward base current

making it unnecessary to expend energy to reverse current

flow as in a series base inductor. Second, there is no base

resistor to limit forward base current and hence no power

loss associated with setting the value of the forward base

current. The process of generating the ramp stores rather

than dissipates energy. Tailoring the amount of energy

stored in T1 to the amount of energy, EB(off), that is required

to turn–off the output transistor results in essentially lossless

operation. [Note: B+ and the primary inductance of T1 (LP)

are chosen such that 1/2 LP Ib2 = EB(off)].

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