ML4425IP 查看數據表（PDF） - Fairchild Semiconductor
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ML4425IP Datasheet PDF : 16 Pages
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PRODUCT SPECIFICATION
CAT
CRT
CRR
TO
SPEED FB
FILTER
ML4425
FB A
FB B
FB C
VDD CAT
750nA
–
1.5V
+
BACK
EMF
SAMPLER
VDD
CRT
750nA
–
1.5V
+
TO RESET INPUT
OF COMMUTATION
STATE MACHINE
CRR
SPEED CVCO
FB
RVCO
VDD
500nA
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
Figure 8. ML4425 Start-up Circuitry for Controlling the Align and Ramp Times
Run Mode (Back EMF Sensing)
At the end of ramp mode the controller goes into run mode.
In run mode, the back EMF sensing is enabled and commuta-
tion is now under the control of the phase locked loop. Motor
speed is now regulated by the speed control loop.
PWM Speed Control
Speed control is accomplished by setting a speed command
at SPEED SET with an input voltage from 0 to 6.9V (VREF).
The accuracy of the speed command is determined by the
external components RVCO and CVCO. There are a number of
methods that can be used to control the speed command of
the ML4425. One is to use a 10kΩ potentiometer from VREF
to ground with the wiper connected to SPEED SET. If
SPEED SET is controlled from a microcontroller, one of its
DACs can be used with VREF as its input reference.
The speed command is compared with the sensed speed from
SPEED FB through a transconductance error amplifier. The
output of the speed error amplifier is SPEED COMP. SPEED
COMP is clamped between one diode drop above 3.9V
(approximately 4.6V) and one diode drop below 1.7V
(approximately 1V) to prevent speed loop “wind-up”. Speed
loop compensation components are connected to this pin as
shown in Figure 9. The speed loop compensation compo-
nents are calculated as follows:
CSC
=
----------2---6---.--9-----×-----N-----×-----V----M-----O----T---O----R-----×-----C----V----C---O-----------
fSB × Ke 2.5 + 98.696 × τm2 × fSB2
(9a)
RSC = 2----π-----×-----f--S-1--B-0----×-----C----S----C-
(9b)
Where fSB is the speed loop bandwidth in Hz.
VREF
10kΩ
RSC
CSC
CT
FROM
SPEED FB
+
–
SPEED SET
3.9V
–
SPEED COMP
+
1.7V
TO
GATING
LOGIC &
OUTPUT
DRIVERS
CT
1.7V
20kHz
PWM ON/OFF
FROM ILIMIT
ONE-SHOT
Figure 9. Speed Control Loop Component Connections
The voltage on SPEED COMP is compared with a ramp
oscillator to create a PWM duty cycle. The PWM ramp oscil-
lator creates a sawtooth function from 1.7V to 3.9V as shown
in Figure 9. A negative clamp at one diode drop below 1.7V
(approximately 1V) starts the oscillator on power up. The
frequency of the ramp oscillator is set by a capacitor to
ground CIOS and is selected using the following equation:
CT = -f----P-------W--I--------M--2----.-×-4----V5---0----µ----A--
(10)
Where fPWM is the PWM frequency in Hz. The PWM duty
cycle from the speed control loop is gated the current limit
one shot that controls the LA, LB, and LC output drivers.
REV. 1.0.2 7/2/01
11
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