ML4425IP 查看數據表（PDF） - Fairchild Semiconductor
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ML4425IP Datasheet PDF : 16 Pages
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ML4425
Pin Configuration
ML4425
28-Pin Narrow PDIP (P28N)
28-Pin SOIC (S28)
ISENSE 1
HA 2
HB 3
HC 4
SPEED COMP 5
CT 6
VREF 7
SPEED SET 8
LA 9
LB 10
LC 11
ILIMIT 12
VCO/TACH 13
VDD 14
28 GND
27 RREF
26 CIOS
25 BRAKE
24 FB C
23 FB B
22 FB A
21 CRR
20 SPEED FB
19 CRT
18 UV FAULT
17 CAT
16 RVCO
15 CVCO
TOP VIEW
PRODUCT SPECIFICATION
Pin Description
Pin
Name
Function
1
ISENSE
Motor current sense input. When ISENSE exceeds 0.2 ↔ ILIMIT, the output drivers LA,
LB, and LC are shut off for a fixed time determined by CIOS.
2
HA
Active low output driver for the phase A high-side switch.
3
HB
Active low output driver for the phase B high-side switch.
4
HC
Active low output driver for the phase C high-side switch.
5
SPEED Speed control loop compensation is set by a series resistor and capacitor from
COMP SPEED COMP to GND.
6
CT
A capacitor from CT to GND sets the PWM oscillator frequency.
VREF
6.9V reference voltage output.
8
SPEED SET Speed loop input which ranges from 0 (stopped) to VREF (maximum speed).
9
LA
Active high output driver for the phase A low-side switch.
10
LB
Active high output driver for the phase B low-side switch.
11
LC
Active high output driver for the phase C low-side switch.
12
ILIMIT
Voltage on this pin sets the ISENSE threshold voltage at 0.2 ↔ ILIMIT, leaving this pin
unconnected selects an internally set threshold.
13
VCO/TACH This TTL level output corresponds to the signal used to clock the commutation state
machine. The output frequency is proportional to the motor speed when the back-
EMF sensing loop is locked onto the rotor position.
14
VDD
12V power supply input.
15
CVCO
A capacitor to GND sets the voltage-to-frequency ratio of the VCO.
2
REV. 1.0.2 7/2/01
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