ML6553 查看數據表（PDF） - Fairchild Semiconductor
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ML6553 Datasheet PDF : 7 Pages
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ML6553
PRODUCT SPECIFICATION
Output Current Capability
The maximum current available at the output of the regulator
is related to the DC resistance of the inductor, the source
impedance of the ML6553, and the desired regulation. The
source impedance of the ML6553 can be estimated at 20mΩ
with an initial output voltage accuracy of ±1%. So the maxi-
mum output current can be estimated using:
IOUT(MAX)
≈
(---D-----E----S----I--R-----E----D-----O----V---A-----–----I---N----I--T----I--A-----L---O----V----A---)-
LDCR + 0.020
×
VTT
So, for an inductor with 11mΩ DC resistance, a termination
voltage of 1.25V, and a desired output voltage accuracy of
3%:
IOUT(MAX)
=
(3% – 1%) × 1.25
-(--0---.--0---1----1----+-----0----.-0----2---0----)---×-----1---0----0--
= 0.806A
(2)
This is enough current capability to terminate 50 bus lines,
assuming 16mA of drive current per line.
Since the feedback loop is closed internally on the ML6553
the total series resistance of the L/C output filter contributes
to increased deviation from no load to full load. The output
source impedance of the ML6553 is approximately 20mΩ.
A 1A load current yields 11mV (from L1) in output
deviation +20mV from the ML6553. Be sure to factor in the
component ESR values when constrained to a particular
maximum output deviation. Adequately bypass the VTT
output with SMD film capacitors to reduce transients
generated by stray lead inductance.
R1
VCCQ
1kΩ
2.5V
VCCQ/2
PVDD
3.3V
C1
0.1µF
C2
0.1µF
GND
R2
100Ω
U1
1
2
3
4
VCCQ
VCCQ/2
AGND
AVCC
DGND
VL
VL
PVDD
8
7
6
5
ML6553
C3
0.1µF
C4
100µF
L1
4.7µH
C5
330µF
OS-CON
VTT
C6
0.1µF
Figure 2. Application Schematic
Figure 3. ML6553 Board Layout
6
REV. 1.0.2 3/21/01
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