MLD1N06CL(2017) 查看數據表（PDF） - ON Semiconductor
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MLD1N06CL Datasheet PDF : 8 Pages
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
4
12
3
SCALE 1:1
A
E
b3
B
4
L3
D
12 3
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
C
A
c2
Z
DETAIL A
H
L4
NOTE 7
b2
c
e
b
SIDE VIEW
TOP VIEW
0.005 (0.13) M C
BOTTOM VIEW
L2
GAUGE
PLANE
H
C
SEATING
PLANE
Z
Z
L
A1
L1
DETAIL A
ROTATED 905 CW
BOTTOM VIEW
ALTERNATE
CONSTRUCTIONS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
3.00
0.118
5.80
0.228
1.60
0.063
6.17
0.243
DATE 21 JUL 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN MAX
A 0.086 0.094
A1 0.000 0.005
b 0.025 0.035
b2 0.028 0.045
b3 0.180 0.215
c 0.018 0.024
c2 0.018 0.024
D 0.235 0.245
E 0.250 0.265
e 0.090 BSC
H 0.370 0.410
L 0.055 0.070
L1 0.114 REF
L2 0.020 BSC
L3 0.035 0.050
L4 −−− 0.040
Z 0.155 −−−
MILLIMETERS
MIN MAX
2.18 2.38
0.00 0.13
0.63 0.89
0.72 1.14
4.57 5.46
0.46 0.61
0.46 0.61
5.97 6.22
6.35 6.73
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
−−− 1.01
3.93 −−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
ǒ Ǔ SCALE 3:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER: 98AON10527D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: DPAK (SINGLE GAUGE)
PAGE 1 OF 1
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