MU9C8148 查看數據表（PDF） - Music Semiconductors

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MU9C8148

SRT Interface

Music Semiconductors 

MU9C8148

PIN DESCRIPTIONS (CONT’D)

Arbitration Signals between two MU9C8148s:

/RQ

(Request, Output, TTL)

are 0000H after a Hardware reset (except for register 04H), all

three-state pins are High-Z, and all TTL output pins will be

HIGH.

The /RQ pin is used to arbitrate access to a shared LANCAM,

and goes LOW when access is required to the LANCAM. /RQ

of one MU9C8148 is connected to /RQI on the other

MU9C8148 to provide notification that a LANCAM access is

pending. One MU9C8148 is configured as Master, and the

other as Slave, to resolve conflicts. /RQ goes HIGH after the

LANCAM interface transactions are completed.

/FULL, /EMPTY (Full/Empty, Output, Open Drain)

If part of the Instruction buffer in the MU9C8148 is configured

as a FIFO, this active-LOW pin can be configured to signal

whether the FIFO is full (all entries contain valid data) or empty

(no entry contains data). The definition of this signal is

programmed in the FIFO Control register.

/RQI (Request Indication, Input, TTL)

/INTEL (HPI Selection, Input, TTL)

If /RQI goes LOW, another MU9C8148 has a request pending

for access to the LANCAM. The LANCAM interface on this chip

is then disabled, and execution of routines is posponed until

/RQI goes HIGH. This pin must be tied HIGH if it is not used.

The /INTEL pin identifies which type of microcontroller is

connected to the Host Processor interface. This pin is set LOW

for Intel-type addressing modes and HIGH for Motorola-type

addressing modes.

Miscellaneous:

VCC, GND (Positive Power Supply and Ground)

/RESET (Hardware Reset, Input, TTL)

Taking /RESET LOW for at least 2 RXC cycles sets the

MU9C8148 to a predefined state. The contents of all registers

These pins are the main power supply connections to the

MU9C8148. VCC must be held at +5V ± 10% relative to the

GND pin, which is at 0V (system reference potential), for

correct operation of the device.

128 Locations

/W, /CM, /EC, S

LANCAM

Interface

D15 - D0

IB

Register

FIFO

Register

Instruction

Pointer and

Control

Start

Address

Address

Pointer

FIFO

Control

Arbiter

TB block

Rev. 5.5 Draft web

TB

Register

Start

Address

Register

Control

Register

FIFO

Control

Register

Figure 1: The Instruction Buffer

4

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