MU9C8148 查看數據表（PDF） - Music Semiconductors

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MU9C8148

SRT Interface

Music Semiconductors 

MU9C8148

INSTRUCTION SET DESCRIPTION (CONT’D)

Instruction:

Wait for match for yyyyB + 4 cycles, if no

match then execute at address

aaaaaaaB.

Binary Op Code: 0010 yyyy raaa aaaa xxx1

y Wait period

r Reserved (set LOW)

a Address

x Don't Care

This instruction waits for a maximum period of yyyyB + 4 clock

cycles for the /MI input to become active, asserting XMATCH

and XFAIL as appropriate. If no match condition occurs during

that period, a branch is executed to the address which is stored

in the “a” bits of the instruction. If a match condition is detected,

execution proceeds to the instruction in the next address.

Instruction:

Move DA part 0 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0000 0ce1

c The state of /CM

e The state of /EC

outputs /CM and /EC at the falling edge of /E for this cycle are

defined by c and e.

Instruction:

Move SA part 2 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0101 0ce1

c The state of /CM

e The state of /EC

This instruction places the most significant part of the SA

address (bits 47–32) on the DQ15–DQ0 lines. The control

outputs /CM and /EC at the falling edge of /E for this cycle are

defined by c and e.

Instruction:

Move data from address aaaaaaaB to

DQ15–DQ0.

Binary Op Code: 0100 rrrr raaa aaaa 0ce1

r Reserved

a Address

c The state of /CM

e The state of /EC

The “Move DA part 0 to DQ15–DQ0” instruction places the

least significant part of the DA address (bits 15–0) on the

DQ15–DQ0 lines. The control outputs /CM and /EC at the

falling edge of /E for this cycle are defined by c and e.

Instruction:

Move DA part 1 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0001 0ce1

c The state of /CM

e The state of /EC

The “Move DA part 1 to DQ15–DQ0” instruction places DA

address bits 31–16 on the DQ15–DQ0 lines. The control

outputs /CM and /EC at the falling edge of /E for this cycle are

defined by c and e.

Instruction:

Move DA part 2 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0010 0ce1

c The state of /CM

e The state of /EC

This instruction places the most significant part of the DA

address (bits 47–32) on the DQ15–DQ0 lines. The control

outputs /CM and /EC at the falling edge of /E for this cycle are

defined by c and e.

The “Move data from address aaaaaaaB to DQ15–DQ0”

instruction places the contents of the address specified by the

“a” bits on the DQ15–DQ0 lines. The control outputs /CM and

/EC at the falling edge of /E for this cycle are defined by c and

e.

Instruction:

Move data from DQ15–DQ0 to address

aaaaaaaB.

Binary Op Code: 0101 rrrr raaa aaaa 1ce1

r Reserved

a Address

c The state of /CM

e The state of /EC

This instruction places the values on the DQ15–DQ0 lines in

the address specified by the “a” bits. The control outputs /CM

and /EC at the falling edge of /E for this cycle are defined by c

and e.

Instruction:

Move data from the FIFO to DQ15–DQ0.

Binary Op Code: 0110 rrrr rrrr rrrr 0ce1

r Reserved

c The state of /CM

e The state of /EC

Instruction:

Move SA part 0 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0011 0ce1

c The state of /CM

e The state of /EC

The “Move data from the FIFO to DQ15–DQ0” instruction

places the contents of the next FIFO location on the

DQ15–DQ0 lines. The control outputs /CM and /EC at the

falling edge of /E for this cycle are defined by c and e.

The “Move SA part 0 to DQ15–DQ0” instruction places the

least significant part of the SA address (bits 15–0) on the

DQ15–DQ0 lines. The control outputs /CM and /EC at the

falling edge of /E for this cycle are defined by c and e.

Instruction:

Move SA part 1 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0100 0ce1

c The state of /CM

e The state of /EC

Instruction:

Move data from DQ15–DQ0 to the FIFO.

Binary Op Code: 0111 rrrr rrrr rrrr 1ce1

r Reserved

c The state of /CM

e The state of /EC

This instruction places the values on the DQ15–DQ0 lines into

the FIFO. The control outputs /CM and /EC at the falling edge

of /E for this cycle are defined by c and e.

The “Move SA part 1 to DQ15–DQ0” instruction places SA

address bits 31–16 on the DQ15–DQ0 lines. The control

Rev. 5.5 Draft web

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