MX25L12845EZNI 查看數據表（PDF） - Macronix International

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MX25L12845EZNI

128M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

Macronix International 

MX25L12845E

DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after specific command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before is-

suing other commands to change data. The WEL bit will return to reset stage under following situations:

- Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP, 4PP) command completion

- Continuously Program mode (CP) instruction completion

- Sector Erase (SE) command completion

- Block Erase (BE, BE32K) command completion

- Chip Erase (CE) command completion

- Single Block Lock/Unlock (SBLK/SBULK) instruction completion

- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from

writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Sig-

nature command (RES).

I. Block lock protection

- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected

as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are

more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protect-

ed Area Sizes".

- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD

bit. If the system goes into four I/O mode, the feature of HPM will be disabled.

- MX25L12845E provides individual block (or sector) write protect & unprotect. User may enter the mode with

WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for

individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with

GBLK instruction and unlock the whole chip with GBULK instruction.

P/N: PM1428

REV. 1.9, SEP. 06, 2013

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