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MX86251 查看數據表(PDF) - Macronix International

零件编号
产品描述 (功能)
生产厂家
MX86251
MCNIX
Macronix International MCNIX
MX86251 Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
connector for
• hardware MPEG-2 decoder using plug-in daughter
card
• Glueless interface to Phillips 7110 for live video input
• Interlaced video can be captured either one field only
or converted to higher resolution non-interlaced frame
• Built in FIFO and flexible decimator
High speed PCI local bus interface
• Support zero wait state PCI burst cycles for maximum
CPU write bandwidth
• Single clock cycle PCI write to frame buffer memory
• level command and data FIFO
Flexible Display Memory configuration
• 1, 2, or 4 MB display memory
• 256K x 4, 256K x 8, and 256K x 16 dual CAS or dual
WE DRAM
• Fast-page and EDO
Fully Integrated for lower system cost
• Integrated 24 bit True Color RAMDAC supports 160
MHz pixel rate and 256x18 look-up table with High
Color and True color bypass
• Dual integrated clock synthesizers
• VESA Display Data Channel (DDC-1/2AB) protocol
support
• Support I2C channel interface
• General purpose I/O pins
"Green PC" power management
• Support VESA DPMS (Display Power Management)
standard
• Built in advanced power management techniques such
as internal DAC power down mode and clock idle
modes
Complete Hardware compatibility
• Windows 95 Plug and Play compliant
• VGA hardware, register, and BIOS level 100%
compatible
• PCI revision 2.1 compatible
P/N:PM0476
2
MX86251
REV. 1.2 , FEB 11, 1998

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