MX86251 查看數據表（PDF） - Macronix International

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MX86251

3D graphic chipset

Macronix International 

MX86251

face) standard. The VMI specifies a 40-pin connector

which, in addition to the VGA connector, contain an 8-bit

YUV pixel bus and an 8-bit Host data bus. The pixel bus

transfers 8-bit packed format YUV pixels from Video de-

coders to the Media port. The host bus transfers com-

pressed MPEG data stream from the Media Port to the

MPEG decoder chip. A small daughter card carrying the

decoder chip plugs into the 40 and 26 pin connectors.

To support the Philips 7110 chip 16-bit YUV pixel format.

the MX86251 Media Port has a special mode where the

VMI host bus pins are used for the upper 8 bits of YUV

pixels.

2.7 True Color RAMDAC

The MX86251 internal 24 bit RAMDAC provides three

256-entry 6-bit word color look-up table (LUT) RAMs feed-

ing three 8-bit DACs for 8-bit per pixel modes. A clock

doubled mode is also provided. A 24 bit LUT bypass is

used in High Color (15/16 bits/pixel) and True Color ( 24

bits/pixel) modes.

The RAMDAC works at pixel clock rate up to 160 MHz.

Many high resolution display modes are possible at this

high pixel clock rate. For example, with a 2 MB card, the

following video mode provides flicker free displays,

2.9 Peripheral Interface ports

The MX86251 has interface ports designed to support

the VESA DDC monitor interface, the I2C channel, and

serial EEPROM.

VESA DDC standard

The VESA DDC (Display Data Channel) standard speci-

fies a two pin serial channel between the display monitor

and the graphics controller. The display monitor sends its

capability and configuration datum to the graphics con-

troller chip for the display driver to set up video display

mode accordingly. Windows 95 Plug'n'Play interface for

display monitors is based on the DDC standard. The

MX86251 provides fully compliant implementation of the

DDC using the DD0 and DD1 pin.

I2C and EEPROM support

The I2C channel is also a two pin serial bus as defined by

Philips. Many video components such as the SA7110

video decoder relies on the I2C channel. The MX86251

provides the SCK and SDA pin for interface to I2C chan-

nel.

1280x1024, 256 color, @80 Hz

1024x768, 64K color, @120 Hz

800x600, 16M color, @120 Hz

2.8 Dual Clock Synthesizers

Some graphics cards are designed to store certain card

configuration or setup information in non-volatile memory

storage. The MX86251 can support such a card using

serial EEPROM. The DD0 and DD1 pin can be pro-

grammed to form an interface to serial EEPROM chips.

The MX86251 contains two phase locked loop (PLL) fre-

quency synthesizers. They generate the dot clock (DCLK)

for display logic and memory clock (MCLK) for memory

controller and graphics engine.

Each PLL scales the input reference frequency to a pro-

grammed clock frequency. The reference frequency

comes from either the crystal oscillator across the XIN

and Xout pin or from a clock input from XIN pin.

The PLL generate its output clock frequency based on

two programmed values, the M and N value, and accord-

ing to the following formula :

f = f * (M+2) / (N+2) * 2R

OUT REF

where R is the 2 bit scale value.

2.10 Power-on Reset Strapping

There are 18 pins, MD[17:0] reserved for strapping.These

MD pins have internal pull-downs.

PFXSWAP, used for 3DFX existence detection, however,

has internal pull-up. If 3DFX is connected, it will drive

PFXSWAP low during reset time. Otherwise, PFXSWAP

will be set to 1 by the internal pull-up.

The function of each power-on strap pin can also be done

through I/O programming. They are defined in registers

3?5/28, 31, and 3FH.

MD5: Reserved

P/N:PM0476

REV. 1.2 , FEB 11, 1998

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