NCP1377BDR2 查看數據表（PDF） - ON Semiconductor
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NCP1377BDR2 Datasheet PDF : 16 Pages
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NCP1377, NCP1377B
Once the power supply has started, the Vcc shall be
constrained below 16 V, which is the maximum rating on
pin 6. Figure 17 portrays a typical NCP1377 startup
sequence with a Vcc regulated at 12.5 V.
13.5
12.5 V
12.5
11.5
10.5
9.50
Regulation
Figure 17. A Typical Startup Sequence
for the NCP1377
Skipping Cycle Mode
The NCP1377 automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18)
and
follows
the
following
formula:
1
2
·
Lp
·
Ip2
·
Fsw
·
Dburst
with:
Lp = Primary inductance
Fsw = Switching frequency within the burst
Ip = Peak current at which skip cycle occurs
Dburst = Burst width/burst recurrence
300
MAX PEAK
CURRENT
200
100
0
WIDTH
RECURRENCE
NORMAL CURRENT
MODE OPERATION
SKIP CYCLE
CURRENT LIMIT
RESET
DRIVER
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 mA
−3
+
2
Rskip
Rsense
+
Figure 18. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise−Free Operation
The skip level selection is done through a simple resistor
inserted between the current sense input and the sense
element. Everytime the NCP1377 output driver goes low,
a 200 mA source forces a current to flow through the sense
pin (Figure 19): when the driver is high, the current source
is off and the current sense information is normally
processed. As soon as the driver goes low, the current
source delivers 200 mA and develops a ground referenced
voltage across Rskip. If this voltage is below the feedback
voltage, the current sense comparator stays in the low state
and the internal latch can be triggered by the next clock
cycle. Now, if because of a low load mode the feedback
Figure 19. A Patented Method Allows for Skip
Level Selection via a Series Resistor Inserted in
Series with the Current
voltage is below Rskip level, then the current sense
comparator permanently resets the latch and the next clock
cycle (given by the demagnetization detection) is ignored:
we are skipping cycles as shown by Figure 18. As soon as
the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1377. To the opposite, in low output power conditions,
no more ringing waves are present on the drain and the
toggling of the current sense comparator alone initiates a
new cycle start. Figure 20 depicts these two different
situations.
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