NJ88C22 查看數據表（PDF） - Zarlink Semiconductor Inc

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NJ88C22

Frequency Synthesiser with resettable counters

Zarlink Semiconductor Inc 

NJ88C22

1

2

3

4

5

CLOCK

ENABLE

DATA

A6

A5

A4

A3

A2

(15)26 (16)27 (17)28

(M2)R2 (M1)R1 (M0)R0

Fig.6 Timing diagram showing programming details

PHASE COMPARATORS

Noise output from a synthesiser loop is related to loop gain:

KPD KVCO

N

where KPD is the phase detector constant (volts/rad), KVCO is

the VCO constant (rad/sec/volt) and N is the overall loop division

ratio. When N is large and the loop gain is low, noise may be

reduced by employing a phase comparator with a high gain.

The sample and hold phase comparator in the NJ88C22 has

a high gain and uses a double sampling technique to reduce

spurious outputs to a low level.

A standard digital phase/frequency detector driving a three-

state output,PDB, provides a ‘coarse’ error signal to enable

fast switching between channels.

The PDB output is active until the phase error is within the

sample and hold phase detector window, when PDB becomes

high impedance. Phase-lock is indicated at this point by a low

level on LD. The sample and hold phase detector provides a

‘fine’ error signal to give further phase adjustment and to hold

the loop in lock. An internally generated ramp, controlled by the

digital output from both the reference and main divider chains,

is sampled at the reference frequency to give the ‘fine’ error

signal, PDA. When in phase lock, this output would be typically

at (VDD2VSS)/2 and any offset from this would be proportional

to phase error.

The relationship between this offset and the phase error is

the phase comparator gain, KPDA, which is programmable with

an external resistor, RB, and a capacitor, CAP. An internal

50pF capacitor is used in the sample and hold comparator.

CRYSTAL OSCILLATOR

When using the internal oscillator, the stability may be

enhanced at high frequencies by the inclusion of a resistor

between the OSC OUT pin and the other components. A value

of between 150Ω and 270Ω is advised, depending on the

crystal series resistance.

PROGRAMMING/POWER UP

Data and signal input pins should not have input applied to

them prior to the application of VDD, as otherwise latch-up may

occur.

5

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