OX12PCI840-PQAG 查看數據表（PDF） - Oxford Semiconductor

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OX12PCI840-PQAG

Integrated Parallel Port and PCI interface

Oxford Semiconductor 

OXFORD SEMICONDUCTOR LTD.

OX12PCI840

CONTENTS

1 PIN INFORMATION ............................................................................................................................... 4

2 PIN DESCRIPTIONS.............................................................................................................................. 5

3 CONFIGURATION & OPERATION ....................................................................................................... 8

4 PCI TARGET CONTROLLER................................................................................................................ 9

4.1 OPERATION ....................................................................................................................................................................... 9

4.2 CONFIGURATION SPACE ................................................................................................................................................. 9

4.2.1 PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 10

4.3 ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 11

4.3.1 PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 11

4.4 ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 12

4.4.1 LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 12

4.4.2 MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 13

4.4.3 LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): .................................................................. 13

4.4.4 LOCAL BUS TIMING PARAMETER/BAR SIZING REGISTER 2 ‘LT2’ (OFFSET 0X0C): ............................................ 14

4.4.5 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X10)................................................ 15

4.5 PCI INTERRUPTS............................................................................................................................................................. 16

4.6 POWER MANAGEMENT .................................................................................................................................................. 17

4.6.1 POWER MANAGEMENT USING MIO.......................................................................................................................... 17

5 BI-DIRECTIONAL PARALLEL PORT ................................................................................................. 18

5.1 OPERATION AND MODE SELECTION ........................................................................................................................... 18

5.1.1 SPP MODE ................................................................................................................................................................... 18

5.1.2 PS2 MODE.................................................................................................................................................................... 18

5.1.3 EPP MODE ................................................................................................................................................................... 18

5.1.4 ECP MODE ................................................................................................................................................................... 18

5.2 PARALLEL PORT INTERRUPT ....................................................................................................................................... 18

5.3 REGISTER DESCRIPTION............................................................................................................................................... 19

5.3.1 PARALLEL PORT DATA REGISTER ‘PDR’ ................................................................................................................. 19

5.3.2 ECP FIFO ADDRESS / RLE ......................................................................................................................................... 19

5.3.3 DEVICE STATUS REGISTER ‘DSR’ ............................................................................................................................ 19

5.3.4 DEVICE CONTROL REGISTER ‘DCR’......................................................................................................................... 20

5.3.5 EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................. 20

5.3.6 EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................. 20

5.3.7 ECP DATA FIFO ........................................................................................................................................................... 20

5.3.8 TEST FIFO .................................................................................................................................................................... 20

5.3.9 CONFIGURATION A REGISTER ................................................................................................................................. 20

5.3.10 CONFIGURATION B REGISTER ................................................................................................................................. 21

5.3.11 EXTENDED CONTROL REGISTER ‘ECR’................................................................................................................... 21

6 SERIAL EEPROM................................................................................................................................ 22

6.1 SPECIFICATION ............................................................................................................................................................... 22

6.2 EEPROM DATA ORGANISATION ................................................................................................................................... 22

6.2.1 ZONE0: HEADER ......................................................................................................................................................... 22

6.2.2 ZONE1: LOCAL CONFIGURATION REGISTERS........................................................................................................ 23

6.2.3 ZONE2: IDENTIFICATION REGISTERS ...................................................................................................................... 23

6.2.4 ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................. 23

6.2.5 ZONE4: FUNCTION ACCESS ...................................................................................................................................... 25

7 OPERATING CONDITIONS................................................................................................................. 26

8 DC ELECTRICAL CHARACTERISTICS ............................................................................................. 26

8.1 NON-PCI I/O BUFFERS.................................................................................................................................................... 26

DS-0021 Jun 05

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