P2V28S20ATP-7 查看數據表（PDF） - Vanguard International Semiconductor
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P2V28S20ATP-7 Datasheet PDF : 51 Pages
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128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command Action
READ with H X X X X
AUTO
PRECHARGE L H H H X
DESEL NOP (Continue Burst to END)
NOP NOP (Continue Burst to END)
L H H L BA
TBST ILLEGAL
READ /
L H L H BA, CA, A10
ILLEGAL
READA
WRITE /
L H L L BA, CA, A10
ILLEGAL
WRITE A
L L H H BA, RA
ACT Bank Active / ILLEGAL*2
L L H L BA, A10
PRE /
PREA
ILLEGAL*2
L L L HX
REFA ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS ILLEGAL
WRITE with H X X X X
AUTO
PRECHARGE L H H H X
DESEL NOP (Continue Burst to END)
NOP NOP (Continue Burst to END)
L H H L BA
TBST ILLEGAL
READ /
L H L H BA, CA, A10
ILLEGAL
READA
WRITE /
L H L L BA, CA, A10
ILLEGAL
WRITEA
L L H H BA, RA
ACT Bank Active / ILLEGAL*2
L L H L BA, A10
PRE /
PREA
ILLEGAL*2
L L L HX
REFA ILLEGAL
L
L
L
L Op-Code,
Mode-Add
MRS ILLEGAL
JULY.2000
Page-9
Rev.2.2
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