P2V28S20ATP-7 查看數據表（PDF） - Vanguard International Semiconductor
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P2V28S20ATP-7 Datasheet PDF : 51 Pages
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128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address
IDLE
H X X XX
Command Action
DESEL NOP
L H H HX
NOP NOP
ROW
ACTIVE
L H H L BA
TBST ILLEGAL*2
READ /
L H L X BA, CA, A10
ILLEGAL*2
WRIT E
L L H H BA, RA
ACT Bank Active, Latch RA
L L H L BA, A10
PRE /
PREA
NOP*4
L L L HX
REFA Auto-Refresh*5
Op-Code,
LLLL
Mode-Add
MRS Mode Register Set*5
H X X XX
DESEL NOP
L H H HX
NOP NOP
L H H L BA
TBST NOP
READ / Begin Read, Latch CA, Determine
L H L H BA, CA, A10
READA Auto-Precharge
WRITE / Begin Write, Latch CA, Determine
L H L L BA, CA, A10
WRITEA Auto-Precharge
L L H H BA, RA
ACT Bank Active / ILLEGAL*2
L L H L BA, A10
PRE /
PREA
Precharge / Precharge All
L L L HX
REFA ILLEGAL
Op-Code,
L
L
L
L Mode-Add
MRS ILLEGAL
JULY.2000
Page-7
Rev.2.2
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