P75N02LD 查看數據表（PDF） - Niko Semiconductor

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P75N02LD

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Niko Semiconductor 

NIKO-SEM

N-Channel Logic Level Enhancement

Mode Field Effect Transistor

P75N02LD

TO-252 (D2PAK)

On-State Drain Current1

Drain-Source On-State

Resistance1

Forward Transconductance1

ID(ON)

RDS(ON)

gfs

VDS = 10V, VGS = 10V

VGS = 10V, ID = 30A

VGS = 7V, ID = 24A

VDS = 15V, ID = 30A

70

5

6

16

A

7

mΩ

8

S

DYNAMIC

Input Capacitance

Ciss

5000

Output Capacitance

Coss

VGS = 0V, VDS = 15V, f = 1MHz

1800

pF

Reverse Transfer Capacitance

Crss

800

Total Gate Charge2

Qg

140

Gate-Source Charge2

Qgs

VDS = 0.5V(BR)DSS, VGS = 10V,

40

nC

Gate-Drain Charge2

Qgd

ID = 35A

75

Turn-On Delay Time2

td(on)

7

Rise Time2

Turn-Off Delay Time2

tr

VDS = 15V, RL = 1Ω

7

nS

td(off)

ID ≅ 30A, VGS = 10V, RGS = 2.5Ω

24

Fall Time2

tf

6

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)

Continuous Current

Pulsed Current3

Forward Voltage1

IS

ISM

VSD

IF = IS, VGS = 0V

75

A

170

1.3 V

Reverse Recovery Time

trr

37

nS

Peak Reverse Recovery Current

IRM(REC)

IF = IS, dlF/dt = 100A / µS

200

A

Reverse Recovery Charge

Qrr

1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％.

2Independent of operating temperature.

3Pulse width limited by maximum junction temperature.

0.043

µC

REMARK: THE PRODUCT MARKED WITH “P75N02LD”, DATE CODE or LOT #

2

AUG-02-2001

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