CMX589A 查看數據表（PDF） - CML Microsystems Plc
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CMX589A Datasheet PDF : 24 Pages
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GMSK Modem
CMX589A
Data Rates
(kbps)
BT = 0.3
R1
C1
4
120kΩ 680pF
4.8
100kΩ 680pF
8
91kΩ
470pF
9.6
91kΩ
390pF
16
47kΩ
470pF
19.2
100kΩ 180pF
32
47kΩ
220pF
38.4 *
47kΩ
180pF
64 *
56kΩ
100pF
80 *
128 *
144 *
160 *
176 *
192 *
* VDD ≥ 4.5V, external clock
BT = 0.5
R1
120kΩ
100kΩ
120kΩ
47kΩ
91kΩ
91kΩ
47kΩ
47kΩ
51kΩ
39kΩ
82kΩ
68kΩ
62kΩ
56kΩ
51kΩ
C1
470pF
470pF
220pF
470pF
150pF
120pF
150pF
120pF
68pF
68pF
22pF
22pF
22pF
22pF
22pF
Table 3: Data Rate vs. BT and Selected External Component Values
Note: In all cases, the value of R1 should not be less than 20.0kΩ, and that the calculated value of C1
includes calculated parasitic capacitance.
2. R3, R4 and C6 form the gain components for the Rx Input signal. R3 should be chosen as required by the
signal input level.
3. For bit rate ≤ 64kbps, R4 = 100kΩ. For bit rate > 64kbps, R4 = 10kΩ.
4. The values chosen for C2 and C3 (including stray capacitance), should be suitable for the applied VDD and
the frequency of X1.
As a guide: C2 = C3 = 33pF at 1.0MHz falling to 18pF at the maximum frequency.
At 3.0V, C2 = C3 = 33pF falling to 18pF at 5.0MHz the equivalent series resistance of X1 should be less
than 2.0KΩ falling to 150Ω at the maximum frequency. Stray capacitance on the Xtal/Clock circuit pins
must be minimized.
5. For bit rate ≤ 64kbps, C6 = 22pF. For bit rate > 64kbps, C6 =
1
3 × bit rate × 2π × 10kΩ
e.g. for 128kbps, C6 = 41.1pF.
6. C7 and C8 should both be .015µF for a data rate of 8kbps, and inversely proportional to the data rate for
other data rates, e.g. 0.030µF at 4kbps, 1800pF at 64kbps, 680pF at 192kbps.
7. The tolerance of C9 is not very critical because it primarily serves as a dc blocking capacitor.
8. The CMX589A can operate correctly with the Xtal frequencies between 1.0MHz and 16.0MHz
(VDD = 5.0V) and 1.0MHz to 5.0MHz (VDD = 3.0V). External clock frequencies up to 25.6MHz (VDD ≥ 4.5V)
are also supported (See Table 4 for examples.) For best results, a crystal oscillator design should drive the
clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally
cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal
manufacturer. Operation of this device without a Xtal or Clock input may cause device damage.
© 1998 Consumer Microcircuits Limited
7
D/589A/3
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