R1100 查看數據表（PDF） - RDC Semiconductor
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R1100 Datasheet PDF : 5 Pages
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RDC®
RISC DSP Communication
R1100
16 Bit RISC Micro Processor
1 Features
l CPU Core
- RDC’s proprietary RISC architecture
- Five-stages pipeline
- Operation frequency: 80MHz
- Support CPU ID
- Supports 32 PIO pins
- External bus, Internal bus and core in the same
clock base
l Bus interface
- Multiplexed address and Data bus
- With 8-bit or 16-bit boot ROM bus size
- Supports direct address bus [A19 : A0]
- 8-bit or 16-bit external bus dynamic access
l ROM/RAM/DRAM Controller and Addressing
Space
- 1M byte memory address space
- 64K byte I/O space
l Software
- Software compatible
microprocessor
with
generic
80C186
l Asynchronous Serial Channels
- Support two Asynchronous serial channels with
hardware handshaking signals.
l Interrupt Controller
- The interrupt controller with seven maskable
external interrupts and one non-maskable
external interrupt (NMI)
l Two Independent DMA Channels
l Integrate PLL(*1~*8)
l Programmable Chip-select Logic
- Programmable chip-select logic for Memory or
I/O bus cycle decoder
l Programmable Wait-state Generator
l Counter/Timers
- Three independent 16-bit timers and one
independent programmable watchdog timer
l Operating Voltage Range
- Operation voltage: 3.3V
- I/O pin input voltage: 3.3V ~ 5V
- I/O pin output voltage: 3.3V
l Package Type
- 100 Pin PQFP & LQFP
l A Green Product
Specifications subject to change without notice, contact your sales representatives for the most update information.
RDC Confidential
Page 2 of 5
REV 1.0 May. 04 2007
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