RF3320 查看數據表（PDF） - RF Micro Devices

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RF3320

CABLE REVERSE PATH PROGRAMMABLE GAIN AMPLIFIER

RF Micro Devices 

Preliminary

Table 1. Serial Interface Control Word Format

Bit

Mnemonic

Description

MSB 6

5

4

3

2

1

LSB 0

D6

Sleep Mode (Software Shutdown)

D5

Gain Control, Bit MSB

D4

Gain Control, Bit 4

D3

Gain Control, Bit 3

D2

Gain Control, Bit 2

D1

Gain Control, Bit 1

D0

Gain Control, Bit LSB

Serial Bus Timing Diagram

TES

TDATAH,TDATAL

TDS TDH

CS

RF3320

3

TWH

TEH

TC

SCLK

SDA

D0

D1

D2

D3

D4

D5

D6

(Data)

Table 2. Timing Data

Parameter

SCLK Pulsewidth

SCLK Period

Setup Time, SDA versus S CLK

Setup Time, CS versus S CLK

Hold Time, SDA versus S CLK

Hold Time, CS versus S CLK

SCLK Pulsewidth, High

SCLK Pulsewidth, Low

Table 3. Programming State

Enter Sleep Mode

Exit Sleep Mode

Enter Shutdown

Exit Shutdown

TX Enable

TX Disable

Symbol

TWH

TC

TDS

TES

TDH

TEH

TDATAH

TDATAL

Min

50

100

10

10

20

20

50

50

Typ

Max

Units

ns

ns

ns

ns

ns

ns

ns

ns

TX

SHDND MSB6

X

H

L

H=High Voltage Logic

X

H

H*

L=Low Voltage Logic

X

L

X

X=Don’t Care

X

H

H*

*Gain Control Data Must be Re-Sent

H

X

X

L

X

X

Rev A10 010514

3-31

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