S3067 查看數據表（PDF） - Unspecified

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S3067

MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC

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S3067

MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC

Table 7. S3067 Receiver Pin Assignment and Descriptions

Pin Name

Level I/O Pin #

Description

RSDP

RSDN

SDLVPECL

Diff.

I

CML

Single

I

Ended

LVPECL

SDTTL

LVTTL I

RSCLKP

RSCLKN

POUT0

POUT1

POUT2

POUT3

POUT4

POUT5

POUT6

POUT7

POUT8

POUT9

POUT10

POUT11

POUT12

POUT13

POUT14

POUT15

POCLKP

POCLKN

OVREF

Diff.

I

CML

Single O

Ended

LVPECL

Diff.

O

LVPECL

DC

O

H15 Differential CML Receive Serial Data stream signals normally

G15 connected to an optical receiver module. Internally biased and

terminated.

N16 LVPECL Signal Detect. LVPECL with internal pull-down. Active

High when SDTTL is held at logic 0. A single-ended 10K LVPECL

input to be driven by the external optical receiver module to

indicate a loss of received optical power. When SDLVPECL is

inactive, the data on the Receive Serial Data In (RSDP/N) pins will

be internally forced to a constant zero. When SDLVPECL is active,

data on the RSDP/N pins will be processed normally. When

SDTTL is to be connected to the optical receiver module instead

of SDLVPECL, then SDLVPECL should be tied High to implement

an active Low Signal Detect, or left unconnected to implement an

active High Signal Detect.

P16 L V T T L S i g n a l D e t e c t . A c t i v e H i g h w h e n S D L V P E C L i s

unconnected (logic 0). Active Low when SDLVPECL is held at

logic 1. A single-ended LVTTL input to be driven by the external

optical receiver module to indicate a loss of received optical

power. When SDTTL is inactive, the data on the RSDP/N pins will

be internally forced to a constant zero. When SDTTL is active,

data on the RSDP/N pins will be processed normally.

L15 Receive Serial Clock. Used to supply a clock input for the RSDP/N

K15 inputs. Internally biased and terminated.

F14 Parallel data output bus, a divide by 16, aligned to the POCLK

E16 parallel output clock. POUT15 is the most significant bit

D16 (corresponding to bit 1 of each PCM word, the first bit received).

E14 POUT0 is the least significant bit. POUT[15:0] is updated on the

C16 falling edge of POCLK.

D15

D14

C15

B15

A14

C13

A13

C12

B12

C11

B11

B10 Parallel Output Clock. A divide by 16, nominally 50% duty cycle,

C10 output clock that is aligned to POUT [15:0] word serial output data.

POUT[15:0] is updated on the falling edge of POCLK.

B14 Single-ended LVPECL reference voltage. Tracks midswing

voltage of parallel output data bus.

10

September 17, 2002/ Revision A

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