S3067 查看數據表（PDF） - Unspecified
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S3067 Datasheet PDF : 27 Pages
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
S3067
S3067 OVERVIEW
The S3067 transceiver implements SONET/SDH
and WDM serialization/deserialization, and transmis-
sion functions. The block diagram in Figure 4 shows
the basic operation of the chip. This chip can be
used to implement the front end of WDM equipment,
which consists primarily of the serial transmit inter-
face and the serial receive interface. The chip
handles all the functions of these two elements, in-
cluding parallel-to-serial and serial-to-parallel
conversion, clock generation, and system timing.
The system timing circuitry consists of management
of the data stream and clock distribution throughout
the front end.
S3067 has the ability to bypass the internal VCO
with an external source and also with the receive
clock. The device generates 14/15, 15/14, 16/17 and
17/16 clocks based upon the received clock and an
external clock to incorporate the FEC capability. The
dividers support the first two rates shown in Table 4.
The S3067 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Table 2. Data Rate Select
RATESEL 0 RATESEL 1 Operating Mode
0
0
OC-3
0
1
OC-12
1
0
OC-24/GBE/FC
1
1
OC-48
Transmitter Operations:
1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Serial input
2. Serial-to-parallel conversion
3. 16-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. S3067 Supports six different code
rates, besides the normal rate, for each of the four
operating modes.
Suggested Interface Devices
AMCC S3076 OC-48 Clock Recovery Device
AMCC S3062 OC-48 Performance Monitor
Table 3. FEC Select
FEC 0
1
2
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
VCO
Divider
17
16
15
14
17
16
15
14
RSCLK
Divider
16
17
14
15
X
X
X
X
Table 4. FEC Modes
Error Correcting Capability
Code Rate showing
Bandwidth Expansion due
to code words & FSB
Example of increased input clock
frequency for STS-48/STM-16 (MHz)
8 bytes per 255-byte block
255/238 = 7.14% increase
155.52*255/238 = 155.52 * 15/14 = 166.63
7 bytes per 255-byte block
255/240 = 6.25% increase
155.52*255/240 = 155.52 * 17/16 = 165.24
6 bytes per 255-byte block
255/242 = 5.37% increase
155.52*255/242 = 163.87
5 bytes per 255-byte block
255/244 = 4.51% increase
155.52*255/244 = 162.53
4 bytes per 255-byte block
255/246 = 3.66% increase
155.52*255/246 = 155.52 * 85/82 = 161.21
3 bytes per 255-byte block
255/248 = 2.82% increase
155.52*255/248 = 159.91
September 17, 2002/ Revision A
3
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