S3067 查看數據表（PDF） - Unspecified

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S3067

MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC

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S3067

MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC

Line Loopback

The line loopback circuitry selects the source of the

data and clock which is output on TSD and TSCLK.

When the Line Loopback Enable input (LLEB) is

high, it selects data and clock from the parallel-to-

serial converter block. When LLEB is low, it forces

the output data multiplexer to select the data and

clock from the RSD and RSCLK inputs, and a re-

ceive-to-transmit loopback can be established at the

serial data rate. Diagnostic loopback and line

loopback can be active at the same time.

Loop Timing

In Serial Loop Timing mode (SLPTIME), the clock

synthesizer PLL of the S3067 is bypassed, and the

timing of the entire transmitter section is controlled

by the Receive Serial Clock, RSCLKP/N. This mode

is entered by setting the SLPTIME input to a TTL

high level.

In this mode, the REFCLKP/N input is not used, and

the RATESEL input is ignored for all transmit func-

tions. It should be carefully noted that the internal

PLL continues to operate in this mode and continues

as the source for the 19MCK and 155MCK. There-

fore these signals are being used (e.g. as the

reference for an external S3076 clock recovery de-

vice), the REFCLKP/N and RATESEL inputs must

be properly driven.

In Reference Loop Timing mode (RLPTIME), the

Parallel Clock from the receiver (POCLK) is used as

the reference clock to the transmitter. In this mode,

the REFCLKP/N input is not used. The 19MCK and

155MCK are generated from the POCLK in this op-

erating mode. When operating the S3067 in

RLPTIME mode, the 19MCK and 155MCK outputs

should not be used as the back-up reference clock

for a clock and data recovery device (S3066,

S3040). When performing loopback testing (DLEB),

the S3067 must not be in RLPTIME.

Squelched Clock Operation

Some integrated optical receiver/clock recovery

modules force their recovered serial receive clock

output to the logic zero state if the optical signal is

removed or reduced below a fixed threshold. This

condition is accompanied by the expected

deassertion of the Signal Detect (SD) output.

The S3067 has been designed for operation with

clock recovery devices that provide continuous serial

clock for seamless downstream clocking in the event

of optical signal loss.

For operation with an optical transceiver that pro-

vides the Squelched Clock behavior as described

above, the S3067 can be operated in the Squelched

Clock mode by activating the SQUELCH pin.

In this condition, the Receive Serial Clock (RSCLKP/N)

is used for all receiver timing when the SDLVPECL/

SDTTL inputs are in the active state. When the

SDLVPECL/SDTTL inputs are placed in the inactive

state (usually by the deassertion of LOCKDET or Sig-

nal Detect from the optical transceiver/clock recovery

unit), the transmitter serial clock will be used to main-

tain timing in the receiver section. This will allow the

POCLK to continue to run and the parallel outputs to

flush out the last received characters and then assume

the all-zero state imposed at the serial data input.

It is important to note that in this mode there will be

a one-time shortening or lengthening of the POCLK

cycle, resulting in an apparent phase shift in the

POCLK at the deassertion of the SD condition. An-

other similar phase shift will occur when the SD

condition is reasserted.

In the normal operating mode, with SQUELCH inac-

tive, there will be no phase discontinuities at the

POCLK output during signal loss or reacquisition

(assuming operation with continuous clocking from

the CRU device such as the AMCC S3076).

8

September 17, 2002/ Revision A

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