S3067 查看數據表（PDF） - Unspecified
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S3067 Datasheet PDF : 27 Pages
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
S3067
Table 6. S3067 Transmitter Pin Assignment and Descriptions
Pin Name
Level I/O Pin #
Description
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
PIN9
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PICLKP
PICLKN
CAP1
CAP2
Single
I
Ended
LVPECL
Internally I
Biased
Diff.
LVPECL
Analog I
A2 Parallel Data Input. A divide-by-16, aligned to the PICLK, parallel
B3 input clock. PIN[15] is the most significant bit (corresponding to
B2 bit 1 of each PCM word, the first bit transmitted). PIN[0] is the
C3 least significant bit (corresponding to bit 16 of each PCM word,
A1 the last bit transmitted). PIN[15:0] is sampled on the rising edge
C2 of PICLK.
B1
D2
E3
C1
E2
F3
F2
E1
F1
G3
A4 Parallel Input Clock. A divide-by-16, nominally 50% duty cycle
A3 input clock, to which PIN[15:0] is aligned. PICLK is used to
transfer the data on the PIN inputs into a holding register in the
parallel-to-serial converter. The rising edge of PICLK samples
PIN[15:0].
R5 Loop Filter Capacitor. The external loop filter capacitor and
T5 resistors are connected to these pins. See Figure 26.
IVREF
DC
I
C4 Single-ended LVPECL input reference voltage.
PHINIT
TSDP
TSDN
TSCLKP
TSCLKN
PCLKP
PCLKN
PHERR
Single
I
Ended
LVPECL
Diff.
O
CML
Diff.
O
CML
Diff.
O
LVPECL
Single O
Ended
LVPECL
G2 Phase Initialization. Rising edge will realign internal timing.
R11 Transmit Serial Data. Differential CML serial data stream signals,
R12 normally connected to an optical transmitter module.
R8 Transmit Serial Clock. Differential CML TSCLKP/N can be used
R9 to retime the TSD signal. This clock frequency will be selected
by RATESEL and FECSEL.
C6 A reference clock generated by dividing the internal bit clock by
B6 16. It is normally used to coordinate word-wide transfers between
upstream logic and the S3067 device.
A5 Phase Error. Pulses High during each PCLK cycle for which there
is a potential set-up/hold timing violation between the internal
byte clock and PICLK timing domains. PHERR is updated on the
falling edge of the PCLK outputs.
September 17, 2002/ Revision A
9
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