HIP4020IB 查看數據表（PDF） - Intersil
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HIP4020IB Datasheet PDF : 9 Pages
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HIP4020
DIRECTION Input Control terminal. The MOS output transistor
pair chosen for conduction is determined by the logic level
applied to the DIRECTION control; resulting in either clockwise
(CW) or counter-clockwise (CCW) shaft rotation.
When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both Q2 and Q4 are
driven high. Current flowing through Q2 (from the motor
terminal OUTA) at the moment of Dynamic Braking will
continue to flow through Q2 to the VSSA and VSSB external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding
(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
flowing through Q4 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
Q4 to the VSSB and VSSA tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
Where VDD to VSS are the Power Supply reference
terminals for the Control Logic, the lowest practical supply
voltage for proper logic control should be no less than 2.0V.
The VSSA and VSSB terminals are separate and
independent from VSS and may be more negative than the
VSS ground reference terminal. However, the maximum
supply level from VDD to VSSA or VSSB must not be greater
than the Absolute Maximum Supply Voltage rating.
Terminals A1, B1, A2, B2, ENA and ENB are internally
connected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level
Converters for TTL or CMOS Input Logic. These inputs are
designed to typically provide ESD protection up to 2kV.
However, these devices are sensitive to electrostatic
discharge. Proper I.C. handling procedures should be
followed.
VDD
INPUT
LEVEL
CONV.
FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION
A1
(DIR)
A2
(BRAKE)
ENA
(ENABLE)
B1
(DIR)
B2
(BRAKE)
ENB
(ENABLE)
VDD
P-DR
LIMIT
Q1
OT AND OC
PROTECT
Q2
N-DR
LIMIT
D1
OUTA
D2
VSSA
VDD
P-DR
LIMIT
Q3
OT AND OC
PROTECT
Q4
N-DR
LIMIT
D3
OUTB
D4
VSSB
FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
6
FN3976.3
December 20, 2005
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