TDA16888 查看數據表（PDF） - Siemens AG

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TDA16888

High Performance Power Combi Controller

Siemens AG 

TDA 16888

3

Functional Block Description

Gate Drive

Both PFC and PWM section use fast totem pole gate drives at pin 8 (PFC OUT) and

pin 10 (PWM OUT) respectively, which are designed to avoid cross conduction currents

and which are equipped with Zener diodes (Z1, Z2) in order to improve the control of the

attached power transistors as well as to protect them against undesirable gate

overvoltages. At voltages below the undervoltage lockout threshold these gate drives are

active low. In order to keep the switching losses of the involved power diodes low and to

minimize electromagnetic emissions, both gate drives are optimized for soft switching

operation. This is achieved by a novel slope control of the rising edge at each driver’s

output (see Figure 13).

Oscillator

The TDA 16888’s clock signals as well as the PFC voltage ramp are provided by the

internal oscillator. The oscillator’s frequency is set by an external resistor connected to

pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is

integrated to guarantee a low current consumption and a high resistance against

electromagnetic interferences. In order to ensure superior precision of the clock

frequency, the clock signal CLK OSC is derived from the minima and maxima of a

triangular instead of a saw-tooth signal (see Figure 18). Furthermore, to provide a clock

reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillator’s clock

signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section

respectively.

The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a

steeply rising edge, the latter of which is triggered by the rising edge of the clock

reference CLK OUT. This ramp has been reversed in contrast to the common practice,

in order to simultaneously allow for current measurement at pin 5 (GND S) and for

external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The

slope of the falling edge, which in conjunction with the output of OP2 controls the pulse-

width-modulation of the PFC output signal VPFC OUT, is derived from the current set by the

external resistor at pin 16 (ROSC). In this way a constant amplitude of the ramp signal

(ca. 4.5 V) is ensured. In contrast, the slope of the rising edge, which marks the minimum

blanking interval and therefore limits the maximum duty cycle ton,max of the PFC output

signal, is determined by an internal current source.

In contrast to the PFC section the ramp signal of the PWM section is trailing edge

triggered with respect to the internal clock reference CLK OUT to avoid undesirable

electromagnetic interference of both sections. Moreover, the maximum duty cycle of the

PWM is limited by the rising edge of the clock reference CLK OUT to 50% to prevent

transformer saturation.

Semiconductor Group

10

Data Sheet 1998-05-06

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