TDA19978AHV 查看數據表（PDF） - NXP Semiconductors.

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TDA19978AHV

Quad HDMI 1.3a receiver interface with equalizer (HDTV up to 1080p, up to UXGA for PC formats)

NXP Semiconductors. 

NXP Semiconductors

TDA19978A

Quad HDMI 1.3a receiver with digital processing

Table 3. Pin description …continued

Symbol

Pin Type[1] Description

VSSH

VDDC(1V8)

VDDC(1V8)

HSDAC

135 G

136 P

137 P

138 I/O

HDMI receiver ground

digital core supply voltage; 1.8 V

digital core supply voltage; 1.8 V

HDMI input/output C HDCP DDC-bus serial data

HSCLC

139 I

HDMI input C HDCP DDC-bus serial clock

HSDAD

140 I/O

HDMI input/output D HDCP DDC-bus serial data

HSCLD

141 I

HDMI input D HDCP DDC-bus serial clock

VDDI(3V3)

RRX2

142 P

143 I

digital inputs supply voltage; 3.3 V

HDMI inputs C and D termination resistance control

VDDH(1V8)

Exposed die pad

144 P

central G

HDMI receiver supply voltage; 1.8 V

exposed die pad; connect to digital core ground (VSSC)

[1] P = power supply; G = ground; I = input; O = output and I/O = input/output.

[2] Connected to the ground of the HDMI receiver (VSSH) in normal operation.

8. Functional description

The TDA19978A converts digital data streams input by the HDMI sources into parallel

digital data for use by media and video signal processing integrated circuits in devices for

HDTV. Data streams can be decoded with or without HDCP protection.

Outputs from the TDA19978A can be RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar

format based on the ITU-R BT.601 standard or YCbCr 4:2:2 based on the ITU-R BT.656

format. Inputs can be both progressive and interlaced formats. The TDA19978A

comprises a color space conversion block, downsampling filters and an embedded timing

code function. In addition, the HDCP repeater function enables other HDMI devices to be

connected to form an extended “total application”.

8.1 Software Drivers

Software drivers are provided for easy configuration and use of the TDA19978A. These

drivers can be integrated with a large range of processors, with or without an operating

system. They control activity detection, input selection, video mode identification, color

conversion, Power-down modes, HDCP and InfoFrame notification.

8.2 HDMI inputs

Control of the four HDMI inputs can be automatic using activity detection or using the

I2C-bus. The HDMI receiver inputs are defined by pins RXx0+, RXx0−, RXx1+, RXx1−,

RXx2+, RXx2−, RXxC+, RXxC−, RRXx, HSCLx and HSDAx. In the pin names, x equals A,

B, C or D (as applicable).

8.3 Termination resistance control

The HDMI receiver input contains a termination resistance control set by an external

resistor connected between pins RRXx and VDDH(3V3). In RRXx, x equals 1 for inputs A

and B or 2 for inputs C and D. Typically, the characteristic impedance is 50 Ω and the

default value of the external terminal control resistor is 12 kΩ ± 1 %.

TDA19978A_3

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 03 — 16 April 2010

© NXP B.V. 2010. All rights reserved.

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