Data Sheet
August 18, 2004
MARS®2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Features
■ One of the next-generation, system-on-a-chip
devices of Agere Systems’ multiservice access &
rate solutions MARSTM family of framers.
■ Transmission convergence and SONET/SDH ter-
minal functionality for linear networks.
■ Versatile IC supports 155/622/2488 Mbits/s
SONET/SDH interface solutions for packet over
SONET (POS), packet over fiber (POF), or asyn-
chronous transfer mode (ATM) applications.
■ Low-power 1.6 V/3.3 V operation.
SONET/SDH Interface
■ Termination of quad STS-3/STM-1,
quad STS-12/STM-4, or single STS-48/STM-16.
■ Supports overhead processing for transport and
path overhead bytes.
■ Optional insertion and extraction of overhead bytes
via serial overhead interface.
■ STS pointer processing to align the receive frame
to the system frame.
■ Support for 1 + 1 and 1:1 linear networks.
■ Full path termination and SPE extraction/insertion.
■ SONET/SDH compliant condition and alarm
reporting.
■ Handles all concatenation levels of STS-3c to
STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.).
■ Built-in diagnostic loopback modes.
■ Compliant with the following Telcordia Technolo-
gies®, ANSI®, and ITU standards:
— GR-253 CORE: SONET Transport Systems:
Common Generic Criteria.
— ITU-T G.707: Network Node Interface for the
Synchronous Digital Hierarchy.
— ITU-T G.803: Architecture of Transport Net-
works Based on the Synchronous Digital Hierar-
chy.
— T1.105: SONET-Basic Description including
Multiplex Structure, Rates, and Formats.
— T1.105.02 SONET-Payload Mappings.
— T1.105.03 SONET-Jitter at Network Interfaces.
— T1.105.06 SONET Physical Layer Specifica-
tions.
— T1.105.07 SONET-Sub-STS-1 Interface Rates
and Formats Specification.
— ITU-T I.432: B-ISDN User-Network Interface-
Physical Layer Specification.
— IETF RFC 2615: PPP over SONET/SDH.
— IETF RFC 1661: The Point-to-Point Protocol
(PPP).
— IETF RFC 1662: PPP in HDLC-like Framing.
Data Processing
■ Provisionable data engine supports payload inser-
tion/extraction for PPP, ATM, or HDLC streams.
■ Extraction and insertion of DS3 frames containing
HDLC or ATM data streams for up to 16 channels.
■ Integrated UTOPIA Level 2 and Level 3 compatible
physical layer interface for packets or ATM cells.
■ Provides/supports internal E3 mapping.
■ Supports DS3/PLCP and clear channel DS3 map-
ping.
■ Insertion and extraction of up to 16 separate data
channels.
■ Direct cell/packet over fiber interface device.
■ Compliant with ATM forum, ITU standards, and
IETF standards.
■ Supports generic framing procedure (GFP) proto-
col.
Interfaces
■ Enhanced UTOPIA interface for cell and packet
transfer.
■ IEEE® 1149.1 port with BIST, scan, and boundry
scan.
Microprocessor Interface
■ Up to 66 MHz synchronous.
■ 16-bit address and 16-bit data interface.
■ Synchronous or asynchronous modes available.
■ Configurable to operate with most commercial
microprocessors.