M-TDAT162G52-3BAL2 查看數據表（PDF） - Agere -> LSI Corporation
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M-TDAT162G52-3BAL2
Agere -> LSI Corporation
M-TDAT162G52-3BAL2 Datasheet PDF : 810 Pages
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Table of Contents
Contents
Page
Features ................................................................................................................................................................... 1
SONET/SDH Interface ....................................................................................................................................... 1
Data Processing................................................................................................................................................. 1
Interfaces ........................................................................................................................................................... 1
Microprocessor Interface ................................................................................................................................... 1
Description.............................................................................................................................................................. 27
Generic Framing Procedure (GFP) .................................................................................................................. 28
Target Applications Supported ............................................................................................................................... 29
MARS2G5 P-Pro (600-Pin LBGA and 792-Pin PBGA) .................................................................................... 29
MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) ........................................................................................... 30
MARS622 P-Pro (TDAT12622) (792-Pin PBGA) ............................................................................................. 31
Overview................................................................................................................................................................. 32
Clocking ........................................................................................................................................................... 34
MARS2G5 P-Pro (792-Pin PBGA) Low-Speed Devices Available......................................................................... 36
MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) ........................................................................................... 36
MARS622 P-Pro (TDAT12622) (792-Pin PBGA) ............................................................................................. 36
MARS2G5 P-Pro Device Product Line Table Summaries...................................................................................... 37
Pin Information ....................................................................................................................................................... 38
792-Pin PBGA Pin Assignments ...................................................................................................................... 38
600-Pin LBGA Pin Assignments ...................................................................................................................... 87
Pin Descriptions...................................................................................................................................................... 97
Microprocessor (MPU) Interface........................................................................................................................... 123
Device Address Space Assignments ............................................................................................................. 123
Microprocessor Interface Modes.................................................................................................................... 124
Microprocessor Interface Timing.................................................................................................................... 125
Necessary Register Provisioning Sequence and Clocks ............................................................................... 133
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers....................................................... 134
Performance Monitor (PM) Reset .................................................................................................................. 158
General-Purpose Input/Output Interface ........................................................................................................ 160
Interrupts ........................................................................................................................................................ 162
Loopback Operation....................................................................................................................................... 163
MPU Register Descriptions ............................................................................................................................ 164
MPU Register Map......................................................................................................................................... 173
Functional Description .......................................................................................................................................... 175
Line Interface........................................................................................................................................................ 176
LVPECL I/O Termination and Load Specifications ........................................................................................ 178
Line Interface I/O Timing................................................................................................................................ 180
Transport Overhead Processor (TOHP-48) Block................................................................................................ 184
Introduction .................................................................................................................................................... 184
TOHP-48 Functional Block Diagram .............................................................................................................. 184
Enhancements ............................................................................................................................................... 186
APSMON and K2MON Processing (Including K1K2 Validation and Pass Through) ..................................... 186
TOHP-48 Receive Direction........................................................................................................................... 187
Transmit Direction (to SONET/SDH line) ....................................................................................................... 197
Receive/Transmit TOHP-48 Interface ............................................................................................................ 204
TOHP-48 Register Descriptions..................................................................................................................... 208
TOHP-48 Register Map ................................................................................................................................. 237
Pointer Processor (PP)......................................................................................................................................... 247
Introduction .................................................................................................................................................... 247
Detailed Description ....................................................................................................................................... 250
PP Register Map Overview ............................................................................................................................ 257
PP Register Descriptions ............................................................................................................................... 258
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Agere Systems Inc.
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