M-TDAT162G52-3BAL2 查看數據表（PDF） - Agere -> LSI Corporation

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M-TDAT162G52-3BAL2

MARS®2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface

Agere -> LSI Corporation 

Data Sheet

August 18, 2004

MARS2G5 P-Pro (TDAT162G52) SONET/SDH

155/622/2488 Mbits/s Data Interface

List of Figures

Figure

Page

Figure 1. MARS2G5 P-Pro Block Diagram ............................................................................................................ 27

Figure 2. GFP Relationship to Transport Payloads ............................................................................................... 28

Figure 3. MARS2G5 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 29

Figure 4. MARS1G2 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 30

Figure 5. MARS622 P-Pro Device Interface Speed/Rate Diagram ....................................................................... 31

Figure 6. MARS2G5 P-Pro External Interfaces ..................................................................................................... 33

Figure 7. Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode ................................................................ 34

Figure 8. Clock Domains in the Packet-Over-Fiber (POF) Mode .......................................................................... 35

Figure 9. PLL Outputs Lock-In Process ............................................................................................................... 122

Figure 10. Microprocessor Interface Synchronous Write Cycle (MPU_MPMODE (Pin D8) = 1) ......................... 125

Figure 11. Microprocessor Interface Synchronous Read Cycle (MPU_MPMODE (Pin D8) = 1) ........................ 127

Figure 12. Microprocessor Interface Asynchronous Write Cycle Description (MPU_MPMODE (Pin D8) = 0) .... 129

Figure 13. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) ................................. 131

Figure 14. PM Reset Signal Generation .............................................................................................................. 159

Figure 15. General Input/Output (GPIO) ............................................................................................................. 161

Figure 16. Interrupt Functionality ......................................................................................................................... 162

Figure 17. Loopback Operation ........................................................................................................................... 163

Figure 18. MARS2G5 P-Pro Block Diagram Indicating the Signal Pins per Block .............................................. 175

Figure 19. Line Interface ...................................................................................................................................... 177

Figure 20. LVPECL Load Connections ................................................................................................................ 179

Figure 21. Receive Line-Side Timing Waveform ................................................................................................. 180

Figure 22. Transmit Line-Side Timing Waveform—OC-48 Contraclocking ......................................................... 181

Figure 23. Transmit Line-Side Timing Waveform—OC-48 Forward Clocking ..................................................... 181

Figure 24. Transmit Line-Side Timing Waveform—Frame Sync ......................................................................... 181

Figure 25. High-Level Block Interconnect ............................................................................................................ 184

Figure 26. TOHP-48 Block Diagram (One Channel) ........................................................................................... 185

Figure 27. Time-Slot Assignments ...................................................................................................................... 194

Figure 28. REI-L (MS-REI) Location .................................................................................................................... 202

Figure 29. RTOH Interface .................................................................................................................................. 205

Figure 30. TTOH Interface ................................................................................................................................... 205

Figure 31. STS-3/STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC Interface Timing ..................... 206

Figure 32. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing .............................................. 206

Figure 33. STS-3/STM-1 Receive TOAC Interface Timing .................................................................................. 207

Figure 34. Signal Degrade and Failure Parameters for BER .............................................................................. 228

Figure 35. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of Pointer Processor ........................ 250

Figure 36. Top Level Block Diagram of the Pointer Processor Block .................................................................. 251

Figure 37. Overview of Pointer Processor Register Map .................................................................................... 257

Figure 38. Path Terminator Block Diagram ......................................................................................................... 345

Figure 39. Block Diagram of SPE Mapper Block ................................................................................................. 346

Figure 40. Direct Mapping into STS SPE ............................................................................................................ 349

Figure 41. STS-Nc SPE ....................................................................................................................................... 349

Figure 42. Asynchronous Mapping of DS3 into STS-1 SPE ................................................................................ 350

Figure 43. Asynchronous Mapping of E3 into STS-1 SPE .................................................................................. 351

Figure 44. STS-48 Frame Structure .................................................................................................................... 352

Figure 45. STS-12 Frame Structure .................................................................................................................... 353

Figure 46. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of STS Receive Terminator ............. 391

Figure 47. STS Receive Terminator (RXT) Functional Block Diagram ............................................................... 392

Figure 48. Interpreter State Machine ................................................................................................................... 394

Figure 49. STS-12 RXT Concatenated Offset Passing ....................................................................................... 398

Figure 50. STS-6 RXT Concatenated Offset Passing ......................................................................................... 398

Figure 51. STS-3 and STS-1 RXT Concatenated Offset Passing ....................................................................... 399

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