M-TDAT162G52-3BAL2 查看數據表（PDF） - Agere -> LSI Corporation

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M-TDAT162G52-3BAL2

MARS®2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface

Agere -> LSI Corporation 

MARS2G5 P-Pro (TDAT162G52) SONET/SDH

155/622/2488 Mbits/s Data Interface

Data Sheet

August 18, 2004

List of Tables

Table

Page

Table 1. List of the Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode.................................................. 34

Table 2. MARS2G5 P-Pro Device Product Line—Data Port Summary.................................................................. 37

Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order ....................................... 38

Table 4. Pin Assignments for 792-Pin PBGA by Signal Name............................................................................... 62

Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order....................................................................... 87

Table 6. Pin Assignments for 600-Pin LBGA by Signal Name ............................................................................... 92

Table 7. Pin Descriptions—Line Interface Signals ................................................................................................. 97

Table 8. Pin Descriptions—TOH Interface Signals............................................................................................... 102

Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals........................................................................ 104

Table 10. Pin Descriptions—Microprocessor Interface Signals............................................................................ 117

Table 11. Pin Descriptions—General-Purpose I/O Signals: Interface Signals ..................................................... 118

Table 12. Pin Descriptions—JTAG Interface Signals ........................................................................................... 119

Table 13. Pin Descriptions—Power Signals ......................................................................................................... 120

Table 14. PLL Test Outputs.................................................................................................................................. 122

Table 15. Pin Descriptions—No-Connect Pins..................................................................................................... 122

Table 16. Leakage Test Pin.................................................................................................................................. 122

Table 17. Device Address Space Assignment ..................................................................................................... 123

Table 18. MPU Modes.......................................................................................................................................... 124

Table 19. Microprocessor Interface Synchronous Write Cycle Specifications ..................................................... 126

Table 20. Microprocessor Interface Synchronous Read Cycle Specifications ..................................................... 128

Table 21. Microprocessor Interface Asynchronous Write Cycle Specifications.................................................... 130

Table 22. Microprocessor Interface Asynchronous Read Cycle Specifications ................................................... 132

Table 23. PM Reset Signal Provisioning .............................................................................................................. 158

Table 24. MPU_VERR[0—5], Version Control Registers (RO) ............................................................................ 164

Table 25. MPU_ISR, Interrupt Status Register (RO or COR/W) .......................................................................... 165

Table 26. MPU_CNDR, Condition Register (RO)................................................................................................. 166

Table 27. MPU_IMR, Interrupt Mask Register (R/W) ........................................................................................... 166

Table 28. MPU_ICLRR, Interrupt Clear Register (R/W) ....................................................................................... 167

Table 29. MPU_SWRSR, Software Reset Register (R/W)................................................................................... 167

Table 30. MPU_GPIO_CTLR, GPIO Output Value (R/W).................................................................................... 168

Table 31. MPU_PROVISION0, Provisioning Register 0 (R/W) ............................................................................ 168

Table 32. MPU_PROVISION1, Provisioning Register 1 (R/W) ............................................................................ 168

Table 33. MPU_LPBKCTLR, Loopback Control Register (R/W) .......................................................................... 169

Table 34. MPU_GPIOCFG, GPIO Configuration Register (R/W)......................................................................... 169

Table 35. MPU_GPIO_OER[1—2], GPIO Output Enable (R/W).......................................................................... 170

Table 36. MPU_PDN1, Powerdown Register 1 (R/W) ......................................................................................... 171

Table 37. MPU_PDN2, Powerdown Register 2 (R/W) ......................................................................................... 171

Table 38. MPU_PDN3, Powerdown Register 3 (R/W) ......................................................................................... 171

Table 39. MPU_SCRATCHR, Scratch Register (R/W)......................................................................................... 171

Table 40. MPU_TDAT16_MODER, MARS2G5 P-Pro Mode Selection Register (R/W)....................................... 171

Table 41. MPU_LI_MODER, Register (R/W) ....................................................................................................... 172

Table 42. MPU_HSI_TST_CTL, High-Speed Interface Control ........................................................................... 172

Table 43. MPU_HSI_LPBKR, High-Speed Interface Loopback Register............................................................. 172

Table 44. MPU Register Map ............................................................................................................................... 173

Table 45. Line Interface Modes ............................................................................................................................ 177

Table 46. Nominal dc Power for Suggested Terminations ................................................................................... 179

Table 47. Receive Line-Side Timing Specifications ............................................................................................. 182

Table 48. Transmit Line-Side Timing Specifications ............................................................................................ 183

Table 49. Framing Bytes Observed for Framing Integrity..................................................................................... 188

Table 50. TOAC Channel Output Versus Time-Slot Assignment ......................................................................... 195

Table 51. Transport Overhead Bytes Received Via RxTOAC Interface............................................................... 196

8

Agere Systems Inc.

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