TFDS4400 查看數據表（PDF） - Vishay Semiconductors

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TFDS4400

SIR Transceiver Module (115.2 kbit/s) 2.7 V to 5.5 V

Vishay Semiconductors 

TFDS4400

Vishay Semiconductors

Recommended SMD Pad Layout

The leads of the device should be soldered in the center position of the pads.

Figure 8. TFDS4400 (Dracula)

Note: Leads of the device should be at least 0.3 mm within the ends of the pads.

Recommended Solder Profile.

Recommended Solder Profile

240

210

180

150

120

90

60

30

0

0

14874

2 - 4°C/s

10 s

max. @

230°C

120 - 180 s

2 - 4°C/s

90 s max.

50 100 150 200 250 300 350

Time ( s )

Figure 9. Recommended Solder Profile

Current Derating Diagram

600

500

400

300

200

100

Current derating as a function of

the maximum forward current of

IRED. Maximum duty cycle: 25%.

14880

0

–40 –20 0

20 40 60 80 100 120 140

Temperature ( 5C )

Figure 10. Current Derating Diagram

www.vishay.com

8 (14)

Document Number 82524

Rev. A1.5, 31-May-00

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