320724-01 查看數據表（PDF） - PANJIT INTERNATIONAL
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320724-01 Datasheet PDF : 16 Pages
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TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
ISA Pin Description
All input (I) and bidirectional (I/O) pins have an internal pull-up resistor between 50 kΩ and 150 kΩ. Pins with names that end in “N” are
active low signals – all others are active high. Open-collector outputs are type “OC.”
Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more
information.
Pin No.(s)
1
2,3,5,6,7,9,10,11
Name(s)
D7_0_OEN
DATA15-8
14
19-15
31,30,29,28,26
20
21,54
52,51,23,22,55
32
33
34
37
38
BHEN_N
ADDR4-0
ADDR9-5
D15_8_OEN
NC
SW9-5
DRQ
DACKN
INTR
AEN_N
IOCHRDY
50,49,47,46,44,
43,42,39
DATA7-0
53
MODE
62
SENSE_8_16N
63
IORN
64
IOWN
66
67
71,74,77,80,88,
89,91,92
70,73,76,79,81,
82,84,85
95
96
98
99
100
4,8,13,25,27,35,41,
45,48,57,61,65,68,72,
75,78,83,86,90,93,97
12,24,36,40,56,58,
59,60,69,87,94
IOCS16N
RESET
DIO8-1N
RENN, ATNN, SRQN,
IFCN, NDACN, NRFDN,
DAVN, EOIN
XTAL0
XTAL1
KEYCLKN
KEYDQ
KEYRSTN
GND
VDD
Type
Description
O
Asserts when DATA7-0 bus is enabled for output – may be left unconnected
I/O
Upper eight bits of bidirectional three-state data bus for transfer of commands,
data, and status between TNT4882 and CPU – can connect directly to the AT bus –
DATA15 is the most significant bit
I
Enables access to upper eight bits of data bus when asserted
I
Determines which register will be accessed during an I/O access
I
Determines if an I/O address is within the range occupied by the TNT4882 –
the chip is selected and an I/O access occurs when ADDR9-5 match SW9-5 and
AEN_N is asserted
O
Asserts when DATA15:8 bus is enabled for output – may be left unconnected
O
Leave unconnected
I
Determines the base address of the TNT4882
O
Asserts to request a DMA transfer cycle
I
Enables FIFO accesses during a DMA transfer cycle
O
Asserts when one or more of the unmasked interrupt conditions becomes true
I
Enables I/O accesses to the TNT4882
OC
When the TNT4882 is not accessed, this open-collector signal is not driven, and a
pull-up resistor on the system board keeps it pulled high – at the start of some
TNT4882 accesses, the TNT4882 may drive it low, then pull it high again during the
cycle to indicate that the TNT4882 is ready for the CPU to end that cycle
I/O
Lower eight bits of bidirectional three-state data bus for transfer of commands, data,
and status between TNT4882 and CPU – can connect directly to the AT bus – DATA7
is the most significant bit
I
Forces the TNT4882 to 7210 (high) or 9914 (low) emulation mode on a hardware
reset – may be left unconnected
I
Pull this pin low to tell the TNT4882 that it is connected to a 16-bit bus – leave it
unconnected if the TNT4882 is connected to an 8-bit bus
I
Drives the contents of the register selected by ADDR4-0 on the data bus when the
TNT4882 is selected
I
The value on the data bus is latched into the register selected by ADDR4-0 on the
rising edge of IOWN when you select the TNT4882
OC
Driven low during an access to the upper data bus
I
Causes a hardware reset and holds the TNT4882 in its idle state while asserted
I/O
8-bit bidirectional IEEE 488 data bus
I/O
IEEE 488 control signals
O
Output of crystal circuit – use only for driving a quartz crystal
I
Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal
O
Strobes data to or from the DS1204 electronic key
I/O
Transmits serial data between the TNT4882 and a DS1204 key
O
Resets a DS1204 key
–
Ground pins – 0 V
–
Power pins – +5 V (±5%)
National Instruments 5
Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com
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