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VG26S17405J-5 查看數據表(PDF) - Vanguard International Semiconductor

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VG26S17405J-5
VML
Vanguard International Semiconductor VML
VG26S17405J-5 Datasheet PDF : 27 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
VIS
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics; 5- Volt Verion
(Ta = 0 to + 70 °C, VCC= + 5V ±10 ,VSS = 0V)
Parameter
Symbol
Test Conditions
Operating current
Low
power
S-version
Standby
Current
Standard
power
version
RAS-only
refresh current
EDO page mode
current
CAS-before-RAS
refresh current
Self-refresh current
(S - Version)
CAS- before- RAS long
refresh current
(S-Version)
ICC1 RAS cycling
CAS, cycling
tRC = min
TTL interface
RAS, CAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS Vcc -0.2V
ICC2 Dout = High-Z
TTL interface
RAS, CAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS Vcc -0.2V
Dout = High-Z
ICC3
RAS cycling, CAS = VIH
tRC = min
ICC4
tRC = min
ICC5
ICC8
tRC = min
RAS, CAS cycling
tRAS 100µs
ICC9
Standby: VCC- 0.2V RAS
CAS before RAS refresh:
2048 cycles / 128ms
RAS, CAS: 0V VIL 0.2V
VCC- 0.2V VIH VIH (Max)
Dout = High-Z, tRAS 300ns
VG26(V)(S)17405
Unit Notes
-5
-6
Min Max Min Max
- 120
- 110 mA 1, 2
-
2
-
2 mA
- 0.25
- 0.25 mA
2
-
2 mA
1
-
1 mA
- 120
- 110 mA 1, 2
- 90
- 120
- 80 mA 1, 3
- 110 mA 1, 2
- 350
- 500
- 350 µA
- 500 µA
Document:1G5-0162
Rev.1
Page 6

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