W9712G8JB 查看數據表（PDF） - Winbond

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产品描述 (功能)

生产厂家

W9712G8JB

4M × 4 BANKS × 8 BIT DDR2 SDRAM

Winbond 

W9712G8JB

3. KEY PARAMETERS

SYM.

SPEED GRADE

Bin(CL-tRCD-tRP)

Part Number Extension

@CL = 7

@CL = 6

tCK(avg) Average clock period

@CL = 5

@CL = 4

@CL = 3

tRCD

tRP

tRC

tRAS

IDD0

IDD1

IDD4R

IDD4W

IDD5B

IDD6

IDD7

Active to Read/Write Command Delay Time

Precharge to Active Command Period

Active to Ref/Active Command Period

Active to Precharge Command Period

Operating current

Operation current (Single bank)

Operating burst read current

Operating burst write current

Burst refresh current

Self refresh current

Operating bank interleave read current

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Min.

Min.

Min.

Max.

Max.

Max.

Max.

Max.

Max.

Max.

DDR2-1066

7-7-7

-18

1.875 nS

7.5 nS

2.5 nS

7.5 nS

3 nS

7.5 nS

3.75 nS

7.5 nS

−

−

13.125 nS

13.125 nS

53.125 nS

40 nS

70 mA

75 mA

120 mA

135 mA

90 mA

6 mA

170 mA

DDR2-800

5-5-5/6-6-6

-25

−

−

2.5 nS

8 nS

2.5 nS

8 nS

3.75 nS

8 nS

5 nS

8 nS

12.5 nS

12.5 nS

52.5 nS

40 nS

65 mA

70 mA

95 mA

120 mA

80 mA

6 mA

140 mA

DDR2-667

5-5-5

-3

−

−

−

−

3 nS

8 nS

3.75 nS

8 nS

5 nS

8 nS

15 nS

15 nS

55 nS

40 nS

60 mA

65 mA

90 mA

115 mA

80 mA

6 mA

130 mA

Publication Release Date: Oct. 12, 2010

-5-

Revision A01

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