HCPL-520K-100 查看數據表（PDF） - Avago Technologies
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HCPL-520K-100 Datasheet PDF : 14 Pages
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Typical Characteristics
All typical values are at TA = 25°C, VCC = 5 V, IF(ON) = 5 mA unless otherwise specified.
Parameter
Symbol
Test Conditions
Typ.
Units
Fig.
Input Current Hysteresis
Input Diode Temperature
Coefficient
IHYS
VCC = 5 V
0.07
mA
3
DVF
IF = 8 mA
-1.25 mV/°C
DTA
Resistance (Input-Output)
RI-O
VI-O = 500 Vdc
1013
W
Capacitance (Input-Output)
CI-O
f = 1 MHz
2.0
pF
Input Capacitance
CIN
VF = 0 V, f = 1 MHz
20
pF
Output Rise Time (10-90%)
tr
45
ns
5, 7
Output Fall Time (90-10%)
tf
10
ns
5, 7
Single Channel Product Only
Output Enable Time to Logic High
tPZH
30
ns
8
Output Enable Time to Logic Low
tPZL
30
ns
8
Output Disable Time from Logic High
tPHZ
45
ns
8
Output Disable Time from Logic Low
tPLZ
55
ns
8
Multi-Channel Product Only
Input-Input Insulation Leakage
Current
Resistance (Input-Input)
II-I
RH ≤ 65%,
0.5
nA
VI-I = 500 V, t = 5 s
RI-I
VI-I = 500 V
1013
W
Capacitance (Input-Input)
CI-I
f = 1 MHz
1.5
pF
Notes
2
2
2, 8
2, 8
2, 10
2
2
9
9
9
Notes:
1. Peak Forward Input Current pulse width < 50 µs at 1 KHz maximum repetition rate.
2. Each channel of a multichannel device.
3. Duration of output short circuit time not to exceed 10 ms.
4. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads or ter�
minals shorted together.
5. This is a momentary withstand test, not an operating condition.
6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8
V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO >
2.0 V).
7. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the
trailing edge of the output pulse.
8. Measured between each input pair shorted together and all output connections for that channel shorted together.
9. Measured between adjacent input pairs shorted together for each multichannel device.
10. Zero-bias capacitance measured between the LED anode and cathode.
11. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25, 125, and –55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
12. Parameters are tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits speci�
fied for all lots not specifically tested.
10
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