74AC174CW 查看數據表（PDF） - Fairchild Semiconductor

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74AC174CW

Hex D-Type Flip-Flop with Master Reset

Fairchild Semiconductor 

Functional Description

Truth Table

The AC/ACT174 consists of six edge-triggered D-type flip-

flops with individual D inputs and Q outputs. The Clock

Inputs

(CP) and Master Reset (MR) are common to all flip-flops.

MR

CP

D

Each D input’s state is transferred to the corresponding flip-

flop’s output following the LOW-to-HIGH Clock (CP) transi-

L

tion. A LOW input to the Master Reset (MR) will force all

H

X



X

H

outputs LOW independent of Clock or Data inputs. The AC/

ACT174 is useful for applications where the true output

H



L

only is required and the Clock and Master Reset are com-

mon to all storage elements.

H

L

X

H = HIGH Voltage Level

L = LOW Voltage Level

= LOW-to-HIGH Transition

X = Immaterial

Logic Diagram

Output

Q

L

H

L

Q

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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