HD74AC174 查看數據表（PDF） - Hitachi -> Renesas Electronics

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HD74AC174

Hex D-Type Flip-Flop with Master Reset

Hitachi -> Renesas Electronics 

HD74AC174

Logic Symbol

D0 D1 D2 D3 D4 D5

CP

MR

Q0 Q1 Q2 Q3 Q4 Q5

Pin Names

D0 to D5

CP

MR

Q0 to Q5

Data Inputs

Clock Pulse Input

Master Reset Input

Outputs

Functional Description

The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The

Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the

corresponding flip-flops’s output following the Low-to-High Clock (CP) transition. A Low input to the

Master Reset (MR) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is

useful for applications where the true output only is required and the Clock and Master Reset are common

to all storage elements.

Truth Table

Inputs

MR

CP

D

L

X

X

H

H

H

L

H

L

X

H : High Voltage Level

L : Low Voltage Level

X : Immaterial

: Low-to-High Transition of Clock

Output

Q

L

H

L

Q

2

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