LTC1174 查看數據表（PDF） - Linear Technology
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LTC1174 Datasheet PDF : 20 Pages
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LTC1174
LTC1174-3.3/LTC1174-5
APPLICATIO S I FOR ATIO
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1174. These items are also illustrated graphically in
the layout diagram in Figure 7. Check the following in your
layout:
1. Is the Schottky catch diode closely connected between
ground (Pin 4) and switch (Pin 5)?
2. Is the “+” plate of CIN closely connected to VIN (Pin 6)?
This capacitor provides the AC current to the internal
P-channel MOSFET.
3. Is the 0.1µF VIN decoupling capacitor closely conected
between VIN (Pin 6) and ground (Pin 4)? This capacitor
carries the high frequency peak currents.
4. Is the SHUTDOWN (Pin 8) actively pulled to VIN during
normal operation? The SHUTDOWN pin is high imped-
ance and must not be allowed to float.
5. Is the IPGM (Pin 7) pulled either to VIN or ground? The
IPGM pin is high impedance and must not be allowed
to float.
DESIGN EXAMPLE
As a design example, assume VIN = 9V (nominal), VOUT =
5V, and IOUT = 350mA maximum. The LTC1174-5 is used
for this application, with IPGM (Pin 7) connected to VIN. The
minmum value of L is determined by assuming the
LTC1174-5 is operating in continuous mode.
IPEAK
AVG CURRENT = IOUT
IV
= IPEAK + IV
2
= 350mA
TIME
1174 F08
Figure 8. Continuous Inductor Current
With IOUT = 350mA and IPEAK = 0.6A (IPGM = VIN), IV =
0.1A.The peak-to-peak ripple inductor current, IRIPPLE, is
0.5A and is also equal to:
( ) IRIPPLE
=
4
•
10−6 ⎛⎝⎜
VOUT +
L
VD ⎞⎠⎟
A P− P
OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
R2
VERSION ONLY
1 VOUT
2 (VFB)
LBOUT
8
SHUTDOWN
7
IPGM
R1
3
6
LBIN LTC1174 VIN
0.1µF +
VIN
CIN
4 GND
SW 5
D
BOLD LINES INDICATE
HIGH CURRENT PATH
COUT
L
VOUT
1174 F07
Figure 7. LTC1174 Layout Diagram (See Board Layout Checklist)
1174fe
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